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FAN3226C Folha de dados(PDF) 9 Page - Fairchild Semiconductor |
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FAN3226C Folha de dados(HTML) 9 Page - Fairchild Semiconductor |
9 / 12 page AN-6069 APPLICATION NOTE © 2007 Fairchild Semiconductor Corporation www.fairchildsemi.com Rev. 1.0.3 • 1/6/10 9 In both these circuits, there is a voltage transient that may last for 50-100ns as the current increases to the limits of the driver. A compact layout using surface mount components keeps the loop area small to minimize parasitic inductance. The two previous circuits require a unique surface mount layout. It is possible to evaluate driver current capability by connecting a relatively large capacitive load on the output of a driver with the simple circuit shown in Figure 21. Figure 21. "Large" Load Test Circuit For a starting point, CLOAD is chosen to be 100 times larger than the load used for rise and fall time measurements and the input is driven with a 1kHz square wave. On typical datasheets, 2A drivers are specified with 1nF load for the rise and fall time specifications, so CLOAD would be selected to be 0.1µF. This relatively large load prevents the output from changing rapidly, allowing the driver output current to reach its internal limiting value. A current probe, IPRB, can be used to monitor the output current along with the output voltage VOUT on an oscilloscope. This enables plotting the output current available at the corresponding output voltage. Bench comparisons have shown that the current measurement obtained using this method agrees closely with that obtained using the clamp circuits in Figure 19 and Figure 20. In addition, the slower current rise and fall times allow the current measurements to be made comfortably within the bandwidth limits of a current probe. Figure 22 shows the waveforms obtained using the test circuit shown in Figure 21 to evaluate a 2A sink / 1.5A source driver (FAN3227C) with a compound output stage. When the driver input, VIN, goes high, there is a transient glitch on the VOUT trace as the output current quickly increases to 3A through the inductance of the current probe loop. After approximately 70ns, the current has reached its peak value and the voltage spike across the parasitic inductances vanishes. With VOUT = 6V, the output current is measured as 1.5A (source current). Figure 22. Compound Driver Current Source Waveforms Figure 22 shows the leading spike across the inductance introduced by the wire loop inserted in the circuit to enable use of a current probe. If the wire loop is removed and the 0.1µF surface mount capacitor is installed in a layout with minimal parasitic inductance, the waveforms shown in Figure 23 are obtained. In short intervals where the voltage waveform is approximately linear, the basic relation is: ⎟ ⎠ ⎞ ⎜ ⎝ ⎛ ⋅ = dT dV C I OUT LOAD (16) can be applied to provide an estimate of the current. Figure 23. Compound Driver Current Estimation The oscillogram in Figure 23 allows calculation of current during the cursor interval as: A 8 . 2 ns 6 . 40 V 131 . 1 µF 1 . 0 I = ⎟ ⎠ ⎞ ⎜ ⎝ ⎛ ⋅ = (17) providing close agreement with the peak value seen in the IOUT trace in Figure 22. A similar calculation around VOUT = 6V provides a current estimation of 1.5A, nearly identical to the result obtained with direct current measurement using a current probe. The close agreement between the current measurement techniques using the large load helps develop confidence in the results obtained. |
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