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FFP08S60S Folha de dados(PDF) 8 Page - Fairchild Semiconductor

Nome de Peças FFP08S60S
Descrição Electrónicos  PFCPWM Combination Controller
Download  17 Pages
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Fabricante Electrônico  FAIRCHILD [Fairchild Semiconductor]
Página de início  http://www.fairchildsemi.com
Logo FAIRCHILD - Fairchild Semiconductor

FFP08S60S Folha de dados(HTML) 8 Page - Fairchild Semiconductor

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AN-8027
© 2009 Fairchild Semiconductor Corporation
www.fairchildsemi.com
Rev. 1.0.0 • 8/26/09
8
,
(1 cos(4
))
D AVG
BOUT
LINE
I
If
t
π
=−
BOUT
I
,
2
BOUT
BOUT RIPPLE
LINE BOUT
I
V
fC
π
=
BOUT
V
,
DAVG
I
D
I
Figure 14. PFC Output Voltage Ripple
(Design Example)
With the ripple specification of
12VPP, the capacitor should be:
,
0.9
239
22
50 12
BOUT
BOUT
LINE
BOUT RIPPLE
I
CF
fV
μ
ππ
>=
=
⋅⋅
Since minimum allowable output voltage during one
cycle line (20ms) drop-outs is 310V, the capacitor
should be:
3
22
2
2
,
2 349 20 10
260
387
310
BOUT
HOLD
BOUT
OUT
OUT MIN
Pt
CF
VV
μ
⋅⋅
×
>=
=
−−
Thus, 270
μF capacitor is selected for the PFC output
capacitor.
[STEP-6] PFC Output Sensing Circuit
To improve system efficiency at low line and light load
condition, FAN480X provides two-level PFC output
voltage. As shown in Figure 15, FAN480X monitors VEA
and VRMS voltages to adjust the PFC output voltage.
The PFC output voltage when 20µA is enabled is given as:
2
2
20
(1
)
2.5
FB
BOUT
BOUT
μAR
VV
-
×
(25)
It is typical second boost output voltage as 340V~300V.
Figure 15. Two-Level PFC Output Block
The voltage divider network for the PFC output voltage
sensing should be designed such that FBPFC voltage is
2.5V at nominal PFC output voltage:
2
12
2.5
FB
BOUT
FB
FB
R
VV
RR
×=
+
(26)
(Design Example)
Assuming the second level of
PFC output voltage is 347V:
2
2
6
6
2.5
(1
)
20 10
347
2.5
(1
)
12.9
387 20 10
BOUT
FB
BOUT
V
R
V
k
=−
×
= −⋅
=
Ω
×
13k
Ω is selected for RFB2.
12
3
(1)
2.5
387
(1) 13 10
1999
2.5
BOUT
FB
FB
V
RR
k
=− ⋅
=
−⋅ ×
=
Ω
2M
Ω is selected for RFB1.
[STEP-7] PFC Current-Sensing Circuit Design
Figure 16 shows the PFC compensation circuits. The first
step in compensation network design is to select the current-
sensing resistor of PFC converter considering the control
window of voltage loop. Since line feed-forward is used in
FAN480X, the output power is proportional to the voltage
control error amplifier voltage as:
0.6
()
0.6
MAX
EA
BOUT
EA
BOUT
SAT
EA
V
PV
P
V
=⋅
(27)
where VEA
SAT is 5.6V and the maximum power limit of PFC
is:
2
.
1
MAX
MAX
LINE BO
M
BOUT
IAC
CS
VG
R
P
RR
=
(28)


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