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FAN3229TMX Folha de dados(PDF) 2 Page - Fairchild Semiconductor |
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FAN3229TMX Folha de dados(HTML) 2 Page - Fairchild Semiconductor |
2 / 25 page © 2007 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN3226 / FAN3227 / FAN3228 / FAN3229 • Rev. 1.0.7 2 Ordering Information Part Number Logic Input Threshold Package Packing Method Quantity per Reel FAN3226CMPX Dual Inverting Channels + Dual Enable CMOS 3x3mm MLP-8 Tape & Reel 3,000 FAN3226CMX SOIC-8 Tape & Reel 2,500 FAN3226TMPX TTL 3x3mm MLP-8 Tape & Reel 3,000 FAN3226TMX SOIC-8 Tape & Reel 2,500 FAN3227CMPX Dual Non-Inverting Channels + Dual Enable CMOS 3x3mm MLP-8 Tape & Reel 3,000 FAN3227CMX SOIC-8 Tape & Reel 2,500 FAN3227TMPX TTL 3x3mm MLP-8 Tape & Reel 3,000 FAN3227TMX SOIC-8 Tape & Reel 2,500 FAN3228CMPX Dual Channels of Two-Input / One-Output Drivers, Pin Configuration 1 CMOS 3x3mm MLP-8 Tape & Reel 3,000 FAN3228CMX SOIC-8 Tape & Reel 2,500 FAN3228TMPX TTL 3x3mm MLP-8 Tape & Reel 3,000 FAN3228TMX SOIC-8 Tape & Reel 2,500 FAN3229CMPX Dual Channels of Two-Input / One-Output Drivers, Pin Configuration 2 CMOS 3x3mm MLP-8 Tape & Reel 3,000 FAN3229CMX SOIC-8 Tape & Reel 2,500 FAN3229TMPX TTL 3x3mm MLP-8 Tape & Reel 3,000 FAN3229TMX SOIC-8 Tape & Reel 2,500 Package Outlines Figure 2. 3x3mm MLP-8 (Top View) Figure 3. SOIC-8 (Top View) Thermal Characteristics(1) Package JL (2) JT (3) JA (4) JB (5) JT (6) Units 8-Lead 3x3mm Molded Leadless Package (MLP) 1.6 68 43 3.5 0.8 °C/W 8-Pin Small Outline Integrated Circuit (SOIC) 40 31 89 43 3.0 °C/W Notes: 1. Estimates derived from thermal simulation; actual values depend on the application. 2. Theta_JL ( JL): Thermal resistance between the semiconductor junction and the bottom surface of all the leads (including any thermal pad) that are typically soldered to a PCB. 3. Theta_JT ( JT): Thermal resistance between the semiconductor junction and the top surface of the package, assuming it is held at a uniform temperature by a top-side heatsink. 4. Theta_JA (ΘJA): Thermal resistance between junction and ambient, dependent on the PCB design, heat sinking, and airflow. The value given is for natural convection with no heatsink using a 2S2P board, as specified in JEDEC standards JESD51-2, JESD51-5, and JESD51-7, as appropriate. 5. Psi_JB ( JB): Thermal characterization parameter providing correlation between semiconductor junction temperature and an application circuit board reference point for the thermal environment defined in Note 4. For the MLP-8 package, the board reference is defined as the PCB copper connected to the thermal pad and protruding from either end of the package. For the SOIC-8 package, the board reference is defined as the PCB copper adjacent to pin 6. 6. Psi_JT ( JT): Thermal characterization parameter providing correlation between the semiconductor junction temperature and the center of the top of the package for the thermal environment defined in Note 4. |
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