250 MHz Bandwidth

DPD Observation Receiver

AD6641

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibilityis assumedbyAnalogDevicesforitsuse,norforanyinfringements of patents or other

rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

www.analog.com

Fax: 781.461.3113

©2011 Analog Devices, Inc. All rights reserved.

FEATURES

Excellent linearity

DNL = ±0.5 LSB typical, INL = ±0.6 LSB typical

Integrated 16k × 12 FIFO

FIFO readback options

12-bit parallel CMOS at 62.5 MHz

6-bit DDR LVDS interface

SPORT at 62.5 MHz

SPI at 25 MHz

High speed synchronization capability

1 GHz full power analog bandwidth

Integrated input buffer

On-chip reference, no external decoupling required

Low power dissipation

695 mW at 500 MSPS

Programmable input voltage range

1.18 V to 1.6 V, 1.5 V nominal

1.9 V analog and digital supply operation

1.9 V or 3.3 V SPI and SPORT operation

Clock duty cycle stabilizer

Integrated data clock output with programmable clock and

data alignment

APPLICATIONS

Wireless and wired broadband communications

Communications test equipment

Power amplifier linearization

GENERAL DESCRIPTION

The AD6641 is a 250 MHz bandwidth digital predistortion

(DPD) observation receiver that integrates a 12-bit 500 MSPS

ADC, a 16k × 12 FIFO, and a multimode back end that allows

users to retrieve the data through a serial port (SPORT), the SPI

interface, a 12-bit parallel CMOS port, or a 6-bit DDR LVDS

port after being stored in the integrated FIFO memory. It is opti-

mized for outstanding dynamic performance and low power

consumption and is suitable for use in telecommunications

applications such as a digital predistortion observation path

where wider bandwidths are desired. All necessary functions,

including the sample-and-hold and voltage reference, are

included on the chip to provide a complete signal conversion

solution.

The on-chip FIFO allows small snapshots of time to be captured

via the ADC and read back at a lower rate. This reduces the

constraints of signal processing by transferring the captured

data at an arbitrary time and at a much lower sample rate. The

FIFO can be operated in several user-programmable modes. In

the single capture mode, the ADC data is captured when sig-

naled via the SPI port or the use of the external FILL± pins. In

the continuous capture mode, the data is loaded continuously

into the FIFO and the FILL± pins are used to stop this operation.

FUNCTIONAL BLOCK DIAGRAM

FIFO

16k × 12

PARALLEL

AND

SPORT

OUTPUTS

SPI CONTROL

AND DATA

REFERENCE

CLOCK AND CONTROL

VIN+

VIN–

VREF

SCLK, SDIO, AND CSB

CLK+

CLK–

DUMP

FILL+

FILL–

EMPTY

SP_SDO

SP_SDFS

SP_SCLK

PD[5:0]± IN DDR LVDS MODE

OR PD[11:0] IN CMOS MODE

PCLK+

FULL

PCLK–

ADC

Figure 1.