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ISLA224P Folha de dados(PDF) 1 Page - Intersil Corporation

Nome de Peças ISLA224P
Descrição Electrónicos  Dual 14-Bit, 250MSPS/200MSPS/130MSPS ADC
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Fabricante Electrônico  INTERSIL [Intersil Corporation]
Página de início  http://www.intersil.com/cda/home
Logo INTERSIL - Intersil Corporation

ISLA224P Folha de dados(HTML) 1 Page - Intersil Corporation

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CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
|Copyright Intersil Americas Inc. 2011. All Rights Reserved
Intersil (and design) and FemtoCharge are trademarks owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
Dual 14-Bit, 250MSPS/200MSPS/130MSPS ADC
ISLA224P
The ISLA224P is a family of dual-channel 14-Bit analog-to-digital
converters. Designed with Intersil’s proprietary FemtoCharge™
technology on a standard CMOS process, the family supports
sampling rates of up to 250MSPS. The ISLA224P is part of a
pin-compatible portfolio of 12-bit and 14-bit dual-channel A/Ds
with maximum sample rates ranging from 130MSPS to
250MSPS.
A serial peripheral interface (SPI) port allows for extensive
configurability, as well as fine control of various parameters such
as gain and offset.
Digital output data is presented in selectable LVDS or CMOS
formats. The ISLA224P is available in a 72-contact QFN package
with an exposed paddle. Operating from a 1.8V supply,
performance is specified over the full industrial temperature
range (-40°C to +85°C).
Key Specifications
• SNR @ 250/200/130MSPS
72.7/73.9/74.7dBFS fIN = 30MHz
70.2/70.7/70.2dBFS fIN = 363MHz
• SFDR @ 250/200/130MSPS
84/86/86dBc fIN = 30MHz
73/75/79dBc fIN = 363MHz
• Total Power Consumption = 837mW @ 250MSPS
Features
• Single Supply 1.8V Operation
• Clock Duty Cycle Stabilizer
• 75fs Clock Jitter
• 700 MHz Bandwidth
• Programmable Built-in Test Patterns
•Multi-ADC Support
- SPI Programmable Fine Gain and Offset Control
- Support for Multiple ADC Synchronization
- Optimized Output Timing
• Nap and Sleep Modes
- 200µs Sleep Wake-up Time
• Data Output Clock
• DDR LVDS-Compatible or LVCMOS Outputs
• User-accessible Digital Temperature Monitor
Applications
• Radar Array Processing
• Software Defined Radios
• Broadband Communications
• High-Performance Data Acquisition
• Communications Test Equipment
DIGITAL
ERROR
CORRECTION
SHA
1.25V
VINBP
VINBN
14-BIT
250 MSPS
ADC
CLOCK
MANAGEMENT
SHA
14-BIT
250 MSPS
ADC
CLKP
CLKN
SPI
CONTROL
VREF
CLKOUTP
CLKOUTN
D[13:0]P
D[13:0]N
ORP
ORN
OUTFMT
OUTMODE
+
VCM
VREF
VINAN
VINAP
+
-
Pin-Compatible Family
MODEL
RESOLUTION
SPEED
(MSPS)
ISLA224P25
14
250
ISLA224P20
14
200
ISLA224P13
14
130
ISLA222P25
12
250
ISLA222P20
12
200
ISLA222P13
12
130
May 19, 2011
FN7570.0


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