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CS1601H Folha de dados(PDF) 11 Page - Cirrus Logic |
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CS1601H Folha de dados(HTML) 11 Page - Cirrus Logic |
11 / 16 page CS1601 DS931PP6 11 5.5 PFC Output Capacitor The value of the PFC output capacitor should be chosen based upon voltage ripple and hold-up requirements. To ensure system stability with the digital controller, the recommended value of the capacitor is within the range of 0.25 F/watt to 0.5F/watt with a Vlink voltage of 460V. 5.6 Output IFB Sense & Input IAC Sense A current proportional to the PFC output voltage, Vlink, is supplied to the IC on pin IFB and is used as a feedback control signal. This current is compared against an internal fixed- value reference current. The ADC is used to measure the magnitude of the IIFB current through resistor RIFB. The magnitude of the IIFB current is then compared to an internal reference current of (Iref) 129A. Figure 18. IFB Input Pin Model Resistor RIFB sets the feedback current and is calculated as follows: By using digital loop compensation, the voltage feedback signal does not require an external compensation network. A current proportional to the AC input voltage is supplied to the IC on pin IAC and is used by the PFC control algorithm. Figure 19. IAC Input Pin Model Resistor RIAC sets the IAC current and is derived as follows: For optimal performance, resistors RIAC & RIFB should use 1% tolerance or better resistors for best Vlink voltage accuracy. 5.7 Valley Switching The zero-current detection (ZCD) pin is monitored for demagnetization in the auxiliary winding of the boost inductor (LB). The ZCD circuit is designed to detect the VAux valley/zero crossings by sensing the voltage transformed onto the auxiliary winding of LB. Figure 20. ZCD Input Pin Model The objective of zero-voltage switching is to initiate each MOSFET switching cycle when its drain-source voltage is at the lowest possible voltage potential, thus reducing switching losses. CS1601 uses an auxiliary winding on the PFC boost inductor to implement zero-voltage switching. Figure 21. Zero-voltage Switch During each switching cycle, when the boost diode current reaches zero, the boost MOSFET drain-source voltage begins oscillating at the resonant frequency of the boost inductor and MOSFET parasitic output capacitance. The ZCD_below_zero signal transitions from high to low just prior to a local minimum of the MOSFET drain-source voltage oscillation. The zero- crossing detect circuit ensures that a ZCD_below_zero pulse will only be generated when the comparator output is continuously high for a nominal time period (tZCB) of 200ns. Therefore, any negative edges on the comparator's output due to spurious glitches will not cause a pulse to be generated. Due to the CS1601's variable-frequency control, the MOSFET switching cycle will not always be initiated at the first resonant IFB VD D 15 k 8 V link CS1601 24k ADC R5 RIFB IFB R6 1 RIFB Vlink VDD – Iref ----------------------------- 460V VDD – 129mA ------------------------------- == [Eq.4] R1 RIAC IAC IA C VD D 15 k 8 V rect CS1601 24 k ADC R2 3 RIAC RIFB = [Eq.5] R3 IAux Vlink ZCD LB R4 CS1601 ZCD_below_zero D2 FE T Drain N:1 + VAux - Demag Comparator + - Vth(ZCD) 5 IZCD Cp ZCD Zero Crossing Detection GD ‘ON’ ZCD_below _zero |
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