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DAC3484 Folha de dados(PDF) 11 Page - Texas Instruments |
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DAC3484 Folha de dados(HTML) 11 Page - Texas Instruments |
11 / 82 page DAC3484 www.ti.com SLAS749A – MARCH 2011 – REVISED JULY 2011 ELECTRICAL CHARACTERISTICS – DIGITAL SPECIFICATIONS (continued) over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT TIMING SYNC INPUT: DACCLKP/N rising edge LATCHING (4) Setup time, SYNCP/N valid ts(SYNC_PLL) to rising edge of 200 ps DACCLKP/N Hold time, SYNCP/N valid th(SYNC_PLL) after rising edge of 300 ps DACCLKP/N TIMING SERIAL PORT Setup time, SDENB to rising ts(SDENB) 20 ns edge of SCLK Setup time, SDIO valid to ts(SDIO) 10 ns rising edge of SCLK Hold time, SDIO valid to th(SDIO) 5 ns rising edge of SCLK Register config6 read (temperature sensor read) 1 µs t(SCLK) Period of SCLK All other registers 100 ns Data output delay after td(Data) 10 ns falling edge of SCLK Minimum RESETB tRESET 25 ns pulsewidth (4) SYNC is required to synchronize the PLL circuit in mulitple devices. The SYNC signal must meet the timing relationship with respect to the reference clock (DACCLKP/N) of the on-chip PLL circuit. Copyright © 2011, Texas Instruments Incorporated 11 |
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