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SM320F2812GHHMEP Folha de dados(PDF) 72 Page - Texas Instruments |
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SM320F2812GHHMEP Folha de dados(HTML) 72 Page - Texas Instruments |
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72 / 158 page  Peripherals 72 March 2004 − Revised April 2010 SGUS051B Figure 4−9 shows the block diagram of the McBSP module with FIFO, interfaced to the F281x and C281x version of Peripheral Frame 2. McBSP Receive Interrupt Select Logic DX DR Expand Logic DRR1 Receive Buffer RX FIFO Interrupt DRR2 Receive Buffer RX FIFO Registers RBR1 Register RBR2 Register McBSP Registers and Control Logic CLKX FSX CLKR FSR 16 Compand Logic DXR2 Transmit Buffer RSR1 XSR2 XSR1 Peripheral Read Bus 16 16 16 16 16 RSR2 DXR1 Transmit Buffer 16 LSPCLK MRINT To CPU McBSP RX Interrupt Logic RX FIFO _15 — RX FIFO _1 RX FIFO _0 RX FIFO _15 — RX FIFO _1 RX FIFO _0 McBSP Transmit Interrupt Select Logic TX FIFO Interrupt TX FIFO Registers MXINT To CPU TX Interrupt Logic 16 16 16 TX FIFO _15 — TX FIFO _1 TX FIFO _0 TX FIFO _15 — TX FIFO _1 TX FIFO _0 Peripheral Write Bus Figure 4−9. McBSP Module With FIFO |
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