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ISL55142IVZ Folha de dados(PDF) 6 Page - Intersil Corporation |
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ISL55142IVZ Folha de dados(HTML) 6 Page - Intersil Corporation |
6 / 14 page 6 FN6230.2 March 1, 2011 Application Information The ISL55141, ISL55142, ISL55143 provide 1, 2 and 4 dual threshold, three-state window comparator(s) in TSSOP or QFN footprints. They offer a combination of speed (10ns Tpd and wide voltage range (18V). This product directly addresses the need for unique common-mode characteristics while supplying a power-down feature. Figures 3 and 4 show the stimulus setup and measurement points for an example propagation delay measurement. Typical room temperature results are displayed in Figure 11. Figure 4 shows a VINP range of 50mV. In Figure 11 the offset is increased in the horizontal axis from 50mV above and below the reference (1.5V) up to 2.5V above and below the 1.5V reference. Two lines are displayed in Figure 11. One represents the rising-to-rising delay (tPDLH) and the other the falling-to-falling delay (tPDHL). Comparator Features These three-state window comparators feature high output current capability, and user defined high and low output levels to interface with a wide variety of logic families. Each receiver comprises two comparators and each comparator has an independent threshold level input, making it easy to implement (Minimum1-VIH)/(Maximum 0-VIL) logic level comparator functions. The CVAX and CVBX pins set the threshold levels of the A and B comparators respectively. VOH and VOL set all the comparator output levels, and VOH must be more positive than VOL. These two inputs are unbuffered supply pins, so the sources driving these pins must provide adequate current for the expected load. VOH and VOL typically connect to the power supplies of the logic device driven by the comparator outputs. The truth table for the receivers is given in Table 1. Receiver outputs are not tri-statable, and do not incorporate any on-chip short circuit current protection. Momentary short circuits to GND, or any supply voltage, will not cause permanent damage, but care must be taken to avoid longer duration short circuits. If tolerable to the application, current limiting resistors can be inserted in series with the QAX and QBX outputs to protect the receiver outputs from damage due to overcurrent conditions. Power-down Features The ISL55141, ISL55142, ISL55143 PD pin provides a means of reducing current consumption when the device is not in use. Supply currents fall from ~7mA to less than 10µA in the power-down mode. The device requires approximately 10µs to power-down and 15µs to power-up. Power Supply Bypassing and Printed Circuit Board Layout As with any high frequency device, good printed circuit board layout is necessary for optimum performance. Ground plane construction is highly recommended, lead lengths should be as short as possible, and the power supply pins must be well bypassed to reduce the risk of oscillation. For normal single supply operation, where the VEE pin is connected to ground, one 0.1µF ceramic capacitor should be placed from the VCC pin to ground. A 4.7µF tantalum capacitor should then be connected from the VCC pin to ground. This same capacitor combination should be placed at each supply pin to ground if split supplies are to be used. Power Dissipation Considerations Specifying continuous data rates, driver loads and driver level amplitudes are key in determining power supply requirements as well as dissipation/cooling necessities. Driver output patterns also impact these needs. The faster the pin activity, the greater the need to supply current and remove heat. FIGURE 3. tPD RECEIVER SWITCHING TEST CIRCUIT FIGURE 4. tPD RECEIVER PROPAGATION DELAY MEASUREMENT POINTS Test Circuits and Waveforms (Continued) + - + - VINP QA QB +11 VCC -3 VEE CVA 1.5V CVB 1.5V +5V-V OH VOL QX 50mV -50mV tPDLH VOH (≈5V) VOL (≈0V) 50% 50% tPDHL VINP 1.5V 1.5V CVA = CVB = 1.5V ISL55141, ISL55142, ISL55143 |
Nº de peça semelhante - ISL55142IVZ |
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Descrição semelhante - ISL55142IVZ |
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