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BD3452KS Folha de dados(PDF) 3 Page - Rohm

Nome de Peças BD3452KS
Descrição Electrónicos  7.1ch Sound Processor
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Fabricante Electrônico  ROHM [Rohm]
Página de início  http://www.rohm.com
Logo ROHM - Rohm

BD3452KS Folha de dados(HTML) 3 Page - Rohm

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Technical Note
3/9
www.rohm.com
2010.06 - Rev.A
© 2010 ROHM Co., Ltd. All rights reserved.
BD3452KS
Timing chart
1) Signal Timing Conditions
Data is read on the rising edge of the clock.
Latch is read on the falling edge of the clock.
Latch signal must terminate with the LOW state.
*To avoid malfunctions, clock and data signals must terminate with the LOW state.
Fig.1
Parameter
Symbol
Limits
Unit
Min.
Typ.
Max.
Minimum Clock Width
twc
1.0
-
-
µs
Minimum Data Width
twd
1.0
-
-
µs
Minimum Latch Width
twl
1.0
-
-
µs
LOW Hold Width
twh
1.0
-
-
µs
Data Set-up Time (DATA
CLK)
tsd
0.5
-
-
µs
Data Hold Time (CLK
DATA)
thd
0.5
-
-
µs
Latch Set-up Time (CLK
LATCH)
tsl
0.5
-
-
µs
Latch Hold Time (DATA
LATCH)
thl
0.5
-
-
µs
Latch Low Set-up Time
ts
0.5
-
-
µs
Latch Low Hold Time
th
0.5
-
-
µs
2) Voltage Conditions for Control Signals
Parameter
Limits
Unit
Conditions
Min.
Typ.
Max.
“H” Input Voltage
2.2
5.5
V
Vcc = 6.5~7.3V
VEE=-6.5~-7.3V
“L” Input Voltage
0
1.0
V
CL
(CLOCK)
DA
DATA
LATCH
thd
thd
th
ts
tsl
thl
tsd
twc
twh
twd
twl
DATA
DATA
LATCH
90%
90%
90%
90%
10%
10%
10%
90%
90%
90%
90%
90%
10%
10%
10%
twc
Terminate with
LOW


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