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GS1503BCVE2 Folha de dados(PDF) 8 Page - Gennum Corporation |
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GS1503BCVE2 Folha de dados(HTML) 8 Page - Gennum Corporation |
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8 / 90 page  GS1503B HD Embedded Audio CODEC Data Sheet 37953 - 1 December 2009 8 of 90 71, 70, 69, 67, 66, 65, 63, 62, 61, 59, 58, 57, 55, 54, 53, 51, 50, 49, 47, 46 VOUT[19:0] O Parallel digital video signal output. VOUT[19] is the MSB and VOUT[0] is the LSB. 74 WCOUTA O 48kHz word clock for channels 1 to 4. Valid only when operating in Demultiplex Mode. 75 WCOUTB O 48kHz word clock for channels 5 to 8. Valid only when operating in Demultiplex Mode. 76 AOUT1/2 O Audio signal output for channels 1 and 2. The AES/EBU digital audio output is bi-phase mark encoded. In both non-AES/EBU modes, the output is not bi-phase mark encoded. 77 AOUT3/4 O Audio signal output for channels 3 and 4. The AES/EBU digital audio output is bi-phase mark encoded. In both non-AES/EBU modes, the output is not bi-phase mark encoded. 78 AOUT5/6 O Audio signal output for channels 5 and 6. The AES/EBU digital audio output is bi-phase mark encoded. In both non-AES/EBU modes, the output is not bi-phase mark encoded. 79 AOUT7/8 O Audio signal output for channels 7 and 8. The AES/EBU digital audio output is bi-phase mark encoded. In both non-AES/EBU modes, the output is not bi-phase mark encoded. 85 DEC_MODE I Demultiplex Mode select. Valid in Demultiplex Mode only. When set HIGH, the GS1503B requires a 48kHz word clock input at WCINA and WCINB. This word clock must be synchronous to the word clock used to embed the audio data. The embedded audio clock phase information in the ancillary data packet will be ignored. See Demultiplex Mode With Word Clock Input on page 73. 87 VCLK I Video clock signal input. 81, 82, 83, 89, 94, 93, 92, 91, 90 CPUADR[8:0] I Host Interface address bus. CPUADR[8] is the MSB and CPUADR[0] is the LSB. In Host Interface Mode B (CPU_SEL set LOW), CPUADR[1:0] are used as the Host Interface control bus. See Table 3-4. 103, 102, 101, 100, 99, 98, 96, 95 CPUDAT[7:0] I/O Host Interface data bus. CPUDAT[7] is the MSB and CPUDAT[0] is the LSB. In Host Interface Mode B (CPU_SEL set LOW), CPUDAT[7:0] are used as the Host Interface address and data bus. 105 CPUCS I Chip select for Host Interface. Active LOW. 106 CPURE I Read enable for Host Interface. Active LOW. In Host Interface Mode B (CPU_SEL set LOW), this input is not used. 107 CPUWE I Write enable for Host Interface. Active LOW. In Host Interface Mode B (CPU_SEL set LOW), this input is used as the Host Interface control enable. 110, 111, 112, 114, 115, 116, 118, 119, 120, 122, 123, 124, 126, 127, 128, 130, 131, 132, 134, 135 VIN[19:0] I Parallel digital video signal input. VIN[19] is the MSB and VIN[0] is the LSB. Table 1-1: Pin Descriptions (Continued) Number Symbol Type Description |
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