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FM24CL64B-GA Folha de dados(PDF) 7 Page - Ramtron International Corporation |
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FM24CL64B-GA Folha de dados(HTML) 7 Page - Ramtron International Corporation |
7 / 12 page FM24CL64B - 64Kb 3V I2C F-RAM (Automotive Temp.) Rev. 1.1 June 2011 Page 7 of 12 To perform a selective read, the bus master sends out the slave address with the LSB set to 0. This specifies a write operation. According to the write protocol, the bus master then sends the address bytes that are loaded into the internal address latch. After the FM24CL64B acknowledges the address, the bus master issues a start condition. This simultaneously aborts the write operation and allows the read command to be issued with the slave address LSB set to a „1‟. The operation is now a current address read. S A Slave Address 1 Data Byte 1 P By Master By F-RAM Start Address Stop Acknowledge No Acknowledge Data Figure 7. Current Address Read S A Slave Address 1 Data Byte 1 P By Master By F-RAM Start Address Stop Acknowledge No Acknowledge Data Data Byte A Acknowledge Figure 8. Sequential Read S A Slave Address 1 Data Byte 1 P By Master By F-RAM Start Address Stop No Acknowledge Data S A Slave Address 0 Address MSB A Start Address Acknowledge Address LSB A Figure 9. Selective (Random) Read |
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