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FM33256 Folha de dados(PDF) 7 Page - Ramtron International Corporation |
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FM33256 Folha de dados(HTML) 7 Page - Ramtron International Corporation |
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7 / 28 page  FM33256/FM3316 SPI Companion w/ FRAM Rev. 2.0 Feb. 2009 Page 7 of 28 In the polled mode, the internal pullup circuit can source a limited amount of current. The maximum capacitance (switch open circuit) allowed on the CNT pin is 100pF. Serial Number A memory location to write a 64-bit serial number is provided. It is a writeable nonvolatile memory block that can be locked by the user once the serial number is set. The 8 bytes of data and the lock bit are all accessed via unique op-codes for the RTC and Processor Companion registers. Therefore the serial number area is separate and distinct from the memory array. The serial number registers can be written an unlimited number of times, so these locations are general purpose memory. However once the lock bit is set, the values cannot be altered and the lock cannot be removed. Once locked the serial number registers can still be read by the system. The serial number is located in registers 10h to 17h. The lock bit is SNL, register 18h bit 7. Setting the SNL bit to a 1 disables writes to the serial number registers, and the SNL bit cannot be cleared. Alarm The alarm function compares user-programmed values to the corresponding time/date values and operates under VDD or VBAK power. When a match occurs, an alarm event occurs. The alarm drives an internal flag AF (register 00h, bit 6) and may drive the ACS pin, if desired, by setting the AL/SW bit (register 18h, bit 6) in the Companion Control register. The alarm condition is cleared by writing a ‘0’ to the AF bit. There are five alarm match fields. They are Month, Date, Hours, Minutes, and Seconds. Each of these fields also has a Match bit that is used to determine if the field is used in the alarm match logic. Setting the Match bit to ‘0’ indicates that the corresponding field will be used in the match process. Depending on the Match bits, the alarm can occur as specifically as one particular second on one day of the month, or as frequently as once per second continuously. The MSB of each Alarm register is a Match bit. Examples of the Match bit settings are shown in Table 3. Selecting none of the match bits (all ‘1’s) indicates that no match is required. The alarm occurs every second. Setting the match select bit for seconds to ‘0’ causes the logic to match the seconds alarm value to the current time of day. Since a match will occur for only one value per minute, the alarm occurs once per minute. Likewise setting the seconds and minutes match select bits causes an exact match of these values. Thus, an alarm will occur once per hour. Setting seconds, minutes, and hours causes a match once per day. Lastly, selecting all match-values causes an exact time and date match. Selecting other bit combinations will not produce meaningful results, however the alarm circuit will follow the functions described. There are two ways a user can detect an alarm event, by reading the AF flag or monitoring the ACS pin. The interrupt pin on the host processor may be used to detect an alarm event. The AF flag in register 00h (bit 6) will indicate that a time/date match has occurred. The AF flag will be set to ‘1’ when a match occurs. The AEN bit must be set to enable the AF flag on alarm matches. The flag and ACS pin will remain in this state until the AF bit is cleared by writing it to a ‘0’. Clearing the AEN bit will prevent further matches from setting AF but will not automatically clear the AF flag. The RTC alarm is integrated into the special function registers and shares its output pin with the 512Hz calibration and square wave outputs. When the RTC calibration mode is invoked by setting the CAL bit (register 00h, bit 2), the ACS output pin will be driven with a 512 Hz square wave and the alarm will continue to operate. Since most users only invoke the calibration mode during production this should have no impact on the otherwise normal operation of the alarm. The ACS output may also be used to drive the system with a frequency other than 512 Hz. The AL/SW bit (register 18h, bit 6) must be ‘0’. A user-selectable frequency is provided by F0 and F1 (register 18h, bits 4 and 5). The other frequencies are 1, 4096, and 32768 Hz. If a continuous frequency output is enabled with CAL mode, the alarm function will not be available. Following is a summary table that shows the relationship between register control settings and the state of the ACS pin. Table 2. State of Register Bit Function of ACS pin CAL AEN AL/SW 0 1 1 /Alarm 0 X 0 Sq Wave out 1 X X 512 Hz out 0 0 1 Hi-Z |
Nº de peça semelhante - FM33256 |
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Descrição semelhante - FM33256 |
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