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LC87F1M16A Folha de dados(PDF) 5 Page - Sanyo Semicon Device

Nome de Peças LC87F1M16A
Descrição Electrónicos  8-bit 1-chip Microcontroller with Full-Speed USB
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Fabricante Electrônico  SANYO [Sanyo Semicon Device]
Página de início  https://www.sanyo-av.com/us/
Logo SANYO - Sanyo Semicon Device

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LC87F1M16A
No.A1909-5/32
Standby Function
• HALT mode: Halts instruction execution while allowing the peripheral circuits to continue operation.
(1) Oscillation is not halted automatically.
(2) There are three ways of resetting the HOLD mode.
1) Setting the reset pin to the lower level
2) Having the watchdog timer or LVD function generate a reset
3) Having an interrupt generated
• HOLD mode: Suspends instruction execution and the operation of the peripheral circuits.
(1) The PLL base clock generator, CF, RC and crystal oscillators automatically stop operation.
Note: The low-speed RC oscillator is controlled directly by the watchdog timer; its oscillation in the standby
mode is also controlled by the watchdog timer.
(2) There are five ways of resetting the HOLD mode.
1) Setting the reset pin to the lower level
2) Having the watchdog timer or LVD function generate a reset
3) Having an interrupt source established at one of the INT0, INT1, INT2, INT4 or INT5 pins
* INT0 and INT1 HOLD mode reset is available only when level detection is set.
4) Having an interrupt source established at port 0
5) Having an bus active interrupt source established in the USB interface circuit
• X'tal HOLD mode: Suspends instruction execution and the operation of the peripheral circuits except the base timer.
(1) The PLL base clock generator, CF and RC oscillator automatically stop operation.
Note: The low-speed RC oscillator is controlled directly by the watchdog timer; its oscillation in the standby
mode is also controlled by the watchdog timer.
(2) The state of crystal oscillation established when the X'tal HOLD mode is entered is retained.
(3) There are six ways of resetting the X'tal HOLD mode.
1) Setting the reset pin to the low level
2) Having the watchdog timer or LVD function generate a reset
3) Having an interrupt source established at either INT0, INT1, INT2, INT4 or INT5
* INT0 and INT1 HOLD mode reset is available only when level detection is set.
4) Having an interrupt source established at port 0
5) Having an interrupt source established in the base timer circuit
6) Having an bus active interrupt source established in the USB interface circuit
Package Form
• SQFP48 (7×7): Lead-/Halogen-free type
Development Tools
• On-chip debugger: TCB87 type-C (one wire communication cable) + LC87F1M16A


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