LC87F7J32A

No.A0886-4/29

Interrupts

• 25 sources, 10 vector addresses

1) Provides three levels (low (L), high (H), and highest (X)) of multiplex interrupt control. Any interrupt requests of

the level equal to or lower than the current interrupt are not accepted.

2) When interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest

level takes precedence over the other interrupts. For interrupts of the same level, the interrupt into the smallest

vector address takes precedence.

No.

Vector Address

Level

Interrupt Source

1

00003H

X or L

INT0

2

0000BH

X or L

INT1

3

00013H

H or L

INT2/T0L/INT4/remote control receiver

4

0001BH

H or L

INT3/INT5/BT0/BT1

5

00023H

H or L

T0H

6

0002BH

H or L

T1L/T1H

7

00033H

H or L

SIO0/UART1 receive

8

0003BH

H or L

SIO1/UART1 transmit

9

00043H

H or L

ADC//T6/T7/PWM4/PWM5

10

0004BH

H or L

Port 0/T4/T5

• Priority levels X > H > L

• Of interrupts of the same level, the one with the smallest vector address takes precedence.

• IFLG (List of interrupt source flag function)

1) Shows a list of interrupt source flags that caused a branching to a particular vector address

(shown in the diagram above).

Subroutine Stack Levels: 512 levels (The stack is allocated in RAM.)

High-speed Multiplication/Division Instructions

• 16 bits × 8 bits

(5 tCYC execution time)

• 24 bits × 16 bits

(12 tCYC execution time)

• 16 bits ÷ 8 bits

(8 tCYC execution time)

• 24 bits ÷ 16 bits

(12 tCYC execution time)

Oscillation Circuits

• RC oscillation circuit (internal):

For system clock

• CF oscillation circuit:

For system clock, with internal Rf

• Crystal oscillation circuit:

For low-speed system clock, with internal Rf

• Frequency variable RC oscillation circuit (internal): For system clock

1) Adjustable in

±4% (typ) step from a selected center frequency.

2) Measures oscillation clock using a input signal from XT1 as a reference.

System Clock Divider Function

• Can run on low current.

• The minimum instruction cycle selectable from 300ns, 600ns, 1.2μs, 2.4μs, 4.8μs, 9.6μs, 19.2μs, 38.4μs,

and 76.8

μs (at a main clock rate of 10MHz).

Internal Reset Function

• Power-On-Reset (POR) function

1) POR resets the system when the power supply voltage is applied.

2) POR release level is selectable from 4 levels (2.07V, 2.37V, 2.87V, 4.35V) by option.

• Low Voltage Detection reset (LVD) function

1) LVD used with POR resets the system when the supply voltage is applied and when it is lowered.

2) LVD function is selectable from enable/disable and the reset level is selectable from 3 levels (2.31V, 2.81V,

4.28V) by option.