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AD5116 Folha de dados(PDF) 8 Page - Analog Devices |
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AD5116 Folha de dados(HTML) 8 Page - Analog Devices |
8 / 24 page AD5111/AD5113/AD5115 Data Sheet Rev. 0 | Page 8 of 24 Parameter Symbol Test Conditions/Comments Min Typ1 Max Unit DYNAMIC CHARACTERISTICS3, 10 Bandwidth BW Code = half scale, −3 dB RAB = 10 kΩ 2 MHz RAB = 80 kΩ 200 kHz Total Harmonic Distortion THD VA = VDD/2 + 1 V rms, VB = VDD/2, f = 1 kHz, code = half scale RAB = 10 kΩ −80 dB RAB = 80 kΩ −85 dB VW Settling Time ts VA = 5 V, VB = 0 V, ±0.5 LSB error band RAB = 10 kΩ 2.7 μs RAB = 80 kΩ 9.5 μs Resistor Noise Density eN_WB Code = half scale, TA = 25°C, f = 100 kHz RAB = 10 kΩ 9 nV/√Hz RAB = 80 kΩ 20 V FLASH/EE MEMORY RELIABILITY3 Endurance11 TA = 25°C 1 MCycles 100 kCycles Data Retention12 50 Years 1 Typical values represent average readings at 25°C, VDD = 5 V, VSS = 0 V, and VLOGIC = 5 V. 2 R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from ideal between successive tap positions. The maximum wiper current is limited to 0.8 × VDD/RAB. 3 Guaranteed by design and characterization; not subject to production test. 4 INL and DNL are measured at VWB with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0 V. DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions. 5 Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on current direction with respect to each other. 6 CA is measured with VW = VA = 2.5 V, CB is measured with VW = VB = 2.5 V, and CW is measured with VA = VB = 2.5 V. 7 Different from operating current; supply current for NVM program lasts approximately 30 ms. 8 Different from operating current; supply current for NVM read lasts approximately 20 μs. 9 PDISS is calculated from (IDD × VDD). 10 All dynamic characteristics use VDD = 5.5 V and VLOGIC = 5 V. 11 Endurance is qualified at 100,000 cycles per JEDEC Standard 22, Method A117 and measured at 150°C. 12 Retention lifetime equivalent at junction temperature (TJ) is 125°C per JEDEC Standard 22, Method A117. Retention lifetime based on an activation energy of 1 eV derates with junction temperature in the Flash/EE memory. |
Nº de peça semelhante - AD5116 |
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Descrição semelhante - AD5116 |
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