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AZP53PG Folha de dados(PDF) 2 Page - Arizona Microtek, Inc |
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AZP53PG Folha de dados(HTML) 2 Page - Arizona Microtek, Inc |
2 / 13 page Arizona Microtek, Inc. AZP53 Low Phase Noise Sine Wave/CMOS to LVPECL Buffer/Divider www.azmicrotek.com +1-480-962-5881 2 Request a Sample May 2012, Rev 2.1 PIN DESCRIPTION AND CONFIGURATION Table 1 - Pin Description Pin Name Type Function 1 Q Output LVPECL Output 2 Q Output LVPECL Output 3 EN Input Enable 4 GND Power Negative Supply 5 D Input Sine or CMOS Input 6 EN_SEL Input Enable Select 7 DIV_SEL Input Divide Select 8 VDD Power Positive Supply 1 Q 3 EN 2 Q 7 DIV_SEL 5 D 6 EN_SEL D3 <Date Code> 8 VDD 4 GND 1 VDD 3 2 GND 4 8 6 7 5 Q EN Q DIV_SEL D EN_SEL Figure 1 - Pin Configuration for QFN8 & SON8, respectively |
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