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CDCE421A Folha de dados(PDF) 5 Page - Texas Instruments |
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CDCE421A Folha de dados(HTML) 5 Page - Texas Instruments |
5 / 27 page DEVICE INFORMATION CE NC SDATA NC NC NC NC VCC VCC NC NC NC 1 2 3 4 5 6 18 17 16 15 14 13 ThermalPad (BottomSide) CDCE421A PIN DESCRIPTIONS CDCE421A www.ti.com..................................................................................................................................................................................................... SCAS873 – APRIL 2009 RGE PACKAGE QFN-24 (TOP VIEW) Table 1. CDCE421A Pin Descriptions TERMINAL TERMINAL ESD TYPE DESCRIPTION NAME NO. PROTECTION Chip enable CE = 1: enable the device and the outputs. CE 1 I Y CE = 0: disable all current sources; in LVDS mode, LVDSP = LVDSN = Hi-Z; in LVPECL mode, LVPECLP = LVPECLN = Hi-Z. GND 8, 9 GND Y Ground 2, 4–6, No connect 11–15, Do not connect these pins. Leave them floating. 18–20, 23,24 High-speed negative differential LVPECL or LVDS outputs. (Outputs are OUTN 7 O Y enabled by CE and selected by the EEPROM configuration registers.) High-speed positive differential LVPECL or LVDS outputs. (Outputs are OUTP 10 O Y enabled by CE and selected by the EEPROM configuration registers.) SDATA 3 I Y Programming pin using TI proprietary interface protocol VCC 16, 17 Power Y 3.3-V power supply In crystal input mode, connect XIN1 to one end of the crystal and XIN2 to the XIN1 21 I Y other end of the crystal. In LVCMOS input single-ended driven mode, XIN1 XIN2 22 GND/NC N (pin 21) acts as an input reference, and XIN2 should connect to GND or it can be left unconnected. Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Link(s): CDCE421A |
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