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SN74ACT2440 Folha de dados(PDF) 7 Page - Texas Instruments |
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SN74ACT2440 Folha de dados(HTML) 7 Page - Texas Instruments |
7 / 33 page SN74ACT2440 NuBus ™ INTERFACE CONTROLLER SCHS010 – D3158, OCTOBER 1988 – REVISED JANUARY 1991 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 cycle descriptions master read cycles When the local board wants to read data from another board connected to the NuBus ™, it first must win mastership of the bus. The timing diagram in Figure 2 shows the simplest form of operation for a typical master read cycle with master ready (MRDY) and master hold tied common with NREQ. The process begins when the local board takes NuBus ™ Request (NREQ) active (low) which causes the local board to begin arbitrating for the bus by forcing RQST low. On the first sample edge after NREQ is taken active (low), the local transfer-mode input lines (LOCTMx) are latched into the controller. Depending on the number of other masters competing for the bus, the requesting process can take a few clock cycles. Under the rules of fair arbitration, each requesting master is guaranteed to win ownership of the bus before a previous winner is allowed to re-arbitrate for the bus. When the local board wins control of the bus, the controller signals the local board by taking NuBus ™ master (NMSTR) active (high). The controller immediately issues a start cycle (if MRDY is active) on the next driving edge by taking START low and placing the read address on the bus. The accessed slave responds to the read request by placing the read data on the bus and driving NuBus ™ acknowledge (ACK) low. The controller signals the local board that the transfer is complete by driving master done (MDONE) active (high). The local board responds to the MDONE signal by driving NREQ, MRDY, and MHOLD inactive (high) when it finishes using the read data. If no other masters are requesting the NuBus ™, the controller parks on the bus, which is indicated by NMSTR remaining high (see Figure 2). The local board can issue another start cycle by simply taking NREQ low; it does not have to perform arbitration when the controller is parked on the bus. The controller remains parked on the bus until another master begins arbitrating for the bus. Refer to the section on NuBus ™ cycles from the parked position for additional details. master write cycles When the local board wants to write data to another board connected to the NuBus ™, it first must win mastership of the bus. Figure 3 shows the timing diagram of a typical master write cycle. The local board follows the same arbitration process as described in the master read cycle. When the local board wins mastership of the bus, the controller signals the local board by driving NMSTR high. The controller immediately issues a start cycle (if MRDY) is active) on the next driving edge by taking START low and placing the write address on the bus. At the end of the start cycle, the controller places the write data on the bus. The addressed slave responds to the write request by driving ACK low. The controller signals the local board that the transfer is complete by driving master done (MDONE) active (high). The cycle is completed on the local board after NREQ, MRDY, and MHOLD return inactive. The same rules apply for parking on the bus as described in the master read cycle. high-speed master read/write cycles Figure 4 demonstrates a high-speed master read or master write cycle. The major difference between these cycles and the ones previously described is that MHOLD does not hold the controller after one master cycle. This feature allows the local board to generate additional start cycles quickly. This capability assumes that no other master has won ownership of the bus and the next transfer cycle (read or write) has not changed. If the transfer cycle has changed, the new transfer code must be latched into the ’ACT2440 by taking NREQ high for one clock cycle immediately after MDONE has been received. If NREQ or MRDY are taken inactive (high) before the first sample clock edge after MDONE has been received, a new start cycle is not automatically generated. Likewise, if MHOLD is taken active (low) before the first sample clock edge after ACK has been received, a new start cycle is not automatically generated. The simplest form of interface ties MHOLD and MRDY in common with NREQ, which guarantees that only one transfer cycle is generated every NREQ cycle. However, higher performance is achievable by using the above method. |
Nº de peça semelhante - SN74ACT2440 |
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Descrição semelhante - SN74ACT2440 |
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