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3 / 23 page www.ti.com Description 1 Description The TPS51916EVM-746 is designed to use a regulated 12-V bus to produce a regulated 1.5-VDDQ output at up to a 20-A load current. The TPS51916EVM-746 demonstrates TPS51916 in a typical DDR3 application with D-CAP2 ™-mode operation. The EVM also provides test points to evaluate the performance of the TPS51916. 1.1 Typical Applications • DDR2/DDR2/DDR3L/DDR4 memory power supplies • SSTL_18, SSTL_15, SSTL_135, and HSTL termination 1.2 Features The TPS51916EVM-746 features: • D-CAP2 ™-mode operation with all-ceramic VDDQ output capacitor • 20-Adc steady-state VDDQ output current • Support VDDQ prebias start-up • SW1 and SW2 provides S3, S5 power control • Optional external VLDOIN voltage for efficiency and flexible operation • Convenient test points for probing critical waveforms 2 Electrical Performance Specifications Table 1. TPS51916EVM-746 Electrical Performance Specifications Parameter Test Conditions Min Typ Max Units Input Characteristics Voltage range VIN 8 12 20 V V5IN 4.5 5 5.5 Maximum input current VIN = 8 V, IVDDQ = 20 A 4.21 A No-load input current Vin = 20 V, IVDDQ = 0 A 0.1 mA VDDQ Output DDR3 (Default setting), R15 = 47.5k, R16 = 2k 1.5 V DDR2, R15 = R16= Open 1.8 V VDDQ Output voltage (VDDQSNS) DDR3L, R15 = 28k, R16 = 2k 1.35 V DDR4, R15 = 18.2k, R16 = 2k 1.2 V VDDQ Output voltage regulation Line regulation (Vin = 8 V –20 V) 0.2% Load regulation (Vin = 12 V, IVDDQ = 0 A–20 A) 0.5% Output voltage ripple Vin = 12 V, IVDDQ = 20 A 20 mVpp Output load current 0 20 A Output overcurrent 30 A Switching frequency 500 kHz Peak efficiency Vin = 12 V, 1.5 VDDQ/8 A 90.93% Full-load efficiency Vin = 12 V, 1.5 VDDQ/20 A 87.3% VTT Output VTT output voltage VTTREF V For DDR2(0.9 VTT) and DDR3(0.75 VTT) –2 2 A VTT output current For DDR3L(0.675 VTT) and DDR4(0.6 VTT) –1.5 1.5 A |IVTT| < 2 A, 1.4 V ≤ VVDDQSNS ≤ 1.8 V –40 40 mV VTT output tolerance to VTTREF |IVTT| < 1.5 A, 1.2 V ≤ VVDDQSNS < 1.4 V –40 40 mV VTTREF Output VTTREF output voltage VDDQSNS/2 V VTTREF output current –10 10 mA 3 SLUU526 – August 2011 Using the TPS51916EVM-746 Complete DDR2, DDR3, DDR3L, and DDR4 Memory Power Solution Synchronous Buck Controller, 2-A LDO, Buffered Submit Documentation Feedback Reference Copyright © 2011, Texas Instruments Incorporated |
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