S0182-01

Switch

Control

Current

Control

FB

SMPS

Q1

Q2

Q3

Q4

Input

Voltage

L1

L2

33µH

V

driver

V

OUT

22µF–470µF

TPIC74101-Q1

www.ti.com

SLIS140

– OCTOBER 2011

a higher than normal ripple and only maintain a 3% tolerance. This ripple and tolerance depends on the loading

and improves with a higher loading condition. When the device is operated with low-power mode active (CLP =

low) and high output currents (

>50 mA), the buck/boost transitioning can cause a reset signal at the RESET pin.

Buck SMPS

(typical), Q2 is turned on for this cycle (synchronized rectification). Otherwise, the current recirculates through Q2

as a free-wheeling diode. The detection for synchronous or asynchronous mode is done cycle-by-cycle.

To avoid a cross-conduction current between Q1 and Q2, an inherent delay is incorporated when switching Q1

off and Q2 on and vice versa.

In buck mode, transistor Q3 is not required and is switched off. Transistor Q4 is switched on to reduce power

dissipation.

The switch timings for transistors Q3 and Q4 are not considered. In buck mode, the logical control of the

transistors does not change.

Figure 2. Buck/Boost Switch Mode Configuration

Boost SMPS

adjusted 5% to 85% depending on the internally sensed voltage of the output. Synchronized rectification occurs

To avoid a discharging of the buffer capacitor, a simultaneous switching on of Q3 and Q4 is not allowed. An

inherent delay is incorporated between Q3 switching off and Q4 switching on and vice versa.

In boost mode, transistor Q2 is not required and remains off. Transistor Q1 is switched on for the duration of the

boost-mode operation (serves as a supply line).

Copyright

© 2011, Texas Instruments Incorporated

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