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TPL0501-100 Folha de dados(PDF) 4 Page - Texas Instruments |
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TPL0501-100 Folha de dados(HTML) 4 Page - Texas Instruments |
4 / 21 page TPL0501 SLIS136A – SEPTEMBER 2011 – REVISED SEPTEMBER 2011 www.ti.com ANALOG SPECIFICATIONS (continued) Typical Values are specified at VDD=5V and operating temperature of 25 C PARAMETER CONDITIONS MIN TYP MAX UNIT TCV Ratiometric temperature coefficient Wiper set at mid-scale 4 ppm/ °C BW Bandwidth Wiper set at mid-scale, TPL0501-100, CLOAD=10pF 265 kHz TSW Wiper settling time TPL0501-100 3 µS VH = 1VRMS at 1kHz, THD Total harmonic distortion 0.005 % VL = VDD/2, measurement at W RHEOSTAT MODE (Measurements between Wi and Li with Hi not connected, or between Wi and Hi with Li not connected) RINL Integral non-linearity –1 1 LSB RDNL Differential non-linearity –0.5 0.5 LSB ROFFSET Offset 0 0.5 2 LSB Code=0x00h, L Floating, Input applied to W, 10 pF RBW Bandwidth 60 kHz on H OPERATING SPECIFICATIONS Typical Values are specified at VDD=5V and operating temperature of 25 C PARAMETER CONDITIONS MIN TYP MAX UNIT IDD(STBY) VDD Standby current 0.3 8 µA IIN-DIG Digital pins leakage current (SCLK, DIN, CS inputs) –1 1 µA Digital Input= 1.8V, VDD=2.7V 5 µA IDD(SUPPL VDD Supply Current Y) Digital Input= 1.8V, VDD=5V 500 µA SERIAL INTERFACE SPECS (SCLK, DIN, CS Inputs) VIH Input high voltage VDD = 2.7 V to 5.5 V 1.8 5.5 V VIL Input low voltage SCLK, DIN, CS Inputs 0 0.6 V CIN Pin capacitance SCLK, DIN, CS Inputs 7 10 pF SPI INTERFACE TIMING CHARACTERISTICS fSCLK SCLK Frequency 25 MHz tSCP SCLK Period 40 ns tSCH SCLK High time 20 ns tSCL SCLK Low time 20 ns tDS DIN to SCLK setup time 5 ns tDH DIN hold after SCLK 5 ns tCSS CS Fall to SCLK rise setup time 15 ns tCSW CS Pulse width high 40 ns 4 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :TPL0501 |
Nº de peça semelhante - TPL0501-100 |
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Descrição semelhante - TPL0501-100 |
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