ISL29120

4

FN8314.0

May 29, 2012

Principles of Operation

Photodiodes and ADC

The ISL29120 contains three photodiode arrays, which convert

light into current. The spectral response for red, green and blue

color ambient intensity sensing is as shown in Figure 2. After

light is converted to current during the light to signal process, the

current output is converted to a digital count by an on-chip

Analog-to-Digital Converter (ADC). The ADC converter resolution

is selectable from 4, 8, 12 or 16 bits. The ADC conversion time is

inversely proportional to the ADC resolution.

The ADC converter uses an integrating architecture. This

conversion method is ideal for converting small signals in the

presence of a periodic noise. A 100ms integration time (16-bit

mode) for instance, rejects 50Hz and 60Hz power line as well as

florescent flicker noise.

The ADC integration time is determined by an internal oscillator

and the n-bit (n = 4, 8, 12, 16) counter inside the ADC. A good

balancing act of integration time and resolution depends on the

application for optimum system performance.

The ADC provides two programmable ranges to dynamically

accommodate different lighting conditions. For dim conditions,

the ADC can be configured at its high sensitivity (low optical)

range. For bright conditions, the ADC can be configured at its low

sensitivity (higher optical) range.

Note that the effective optical sensitivity of the ISL29120 in

integration time.

There are eight 8-bit registers inside the ISL29120 for

configuration, control and status indication. The two command

registers at address 0x00 and 0x01 define the operation of the

device and provide status of the interrupt events. Two 8-bit read

only registers at address 0x02 and 0x03 are for the ADC output.

These registers contain the results of the latest A/D conversion.

Registers 0x04 and 0x05 contain the ‘low threshold’ value and

registers 0x06 and 0x07 store the ‘high threshold’ value for

interrupt generation.

as 1000110x, where x is R (read) or W (write) bit.

Figure 4 shows a sample one-byte read. Figure 5 shows a sample

line, while either the master or the slave can drive the SDA (data)

with the master asserting a start condition (SDA falling while SCL

remains high). The following byte is driven by the master, and

includes the slave address and read/write bit. The receiving device

is responsible for pulling SDA low during the acknowledgement

condition (SDA rising while SCL remains high).

START

W A

A

A6 A5 A4 A3 A2 A1 A0 W A R7 R6 R5 R4 R3 R2 R1 R0 A

A6 A5 A4 A3 A2 A1 A0 W A

A

A

A D7D6 D5 D4 D3 D2D1 D0

13

5

7

13

57

12 3

4 5

6

9

2

4

6

STOP START

SDA DRIVEN BY MASTER

DEVICE ADDRESS

SDA DRIVEN BY ISL29120

DATA BYTE0

REGISTER ADDRESS

OUT

DEVICE ADDRESS

SDA DRIVEN BY MASTER

SDA DRIVEN BY MASTER

24

68 9

2468 9

7

8

1

357

8

9

IN

START

W

A

A

A6 A5 A4 A3 A2 A1 A0 W

A R7 R6 R5 R4 R3 R2 R1 R0 A B7 B6 B5 B4 B3 B2 B1 B0

A

A

1

2

615

948

STOP

SDA DRIVEN BY MASTER

FUNCTIONS

REGISTER ADDRESS

DEVICE ADDRESS

SDA DRIVEN BY MASTER

SDA DRIVEN BY MASTER

AA

34

5

7

8

9

2

3

4

6

7

8

1

2

3

5

67

9

A