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TSC2046E-Q1 Folha de dados(PDF) 2 Page - Texas Instruments |
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TSC2046E-Q1 Folha de dados(HTML) 2 Page - Texas Instruments |
2 / 28 page CDAC Internal 2.5V Reference SAR TSC2046E Comparator 6−Channel MUX Serial Data In/Out T e m pe ra ture Se n s or P e n D e tec t Battery Monitor DOUT BUSY CS DCLK DIN VBAT AUX V RE F +V CC IOVDD X+ X− Y+ Y− PENIRQ TSC2046E-Q1 SBAS510 – JUNE 2010 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. TERMINAL FUNCTIONS TERMINAL DESCRIPTION NAME NO. +VCC 1 Power supply X+ 2 X+ position input Y+ 3 Y+ position input X- 4 X- position input Y- 5 Y- position input GND 6 Ground VBAT 7 Battery monitor input AUX 8 Auxiliary input to ADC VREF 9 Voltage reference input/output IOVDD 10 Digital I/O power supply PENIRQ 11 Pen interrupt DOUT 12 Serial data output. Data are shifted on the falling edge of DCLK. This output is high impedance when CS is high. BUSY 13 Busy output. This output is high impedance when CS is high. DIN 14 Serial data input. If CS is low, data sre latched on the rising edge of DCLK. Chip select input. Controls conversion timing and enables the serial input/output register. CS 15 CS high = power-down mode (ADC only). DCLK 16 External clock input. This clock runs the SAR conversion process and synchronizes serial data I/O. 2 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TSC2046E-Q1 |
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Descrição semelhante - TSC2046E-Q1 |
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