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TPIC1321L Folha de dados(PDF) 4 Page - Texas Instruments |
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TPIC1321L Folha de dados(HTML) 4 Page - Texas Instruments |
4 / 14 page TPIC1321L 3HALF HBRIDGE GATEPROTECTED LOGICLEVEL POWER DMOS ARRAY SLIS042 − NOVEMBER 1994 2−4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 resistive-load switching characteristics, TC = 25°C PARAMETER TEST CONDITIONS MIN TYP MAX UNIT td(on) Turn-on delay time 34 70 td(off) Turn-off delay time VDD = 25 V, RL = 40 Ω, ten = 10 ns, 80 150 ns tr Rise time VDD = 25 V, tdis = 10 ns, RL = 40 Ω, See Figure 2 ten = 10 ns, 28 55 ns tf Fall time tdis = 10 ns, See Figure 2 15 30 Qg Total gate charge VDS = 48 V, ID = 625 mA, VGS = 5 V, 4.6 5.8 Qgs(th) Threshold gate-to-source charge VDS = 48 V, See Figure 3 ID = 625 mA, VGS = 5 V, 0.7 0.88 nC Qgd Gate-to-drain charge See Figure 3 2.5 3.13 nC LD Internal drain inductance 5 nH LS Internal source inductance 5 nH Rg Internal gate resistance 0.25 Ω thermal resistance PARAMETER TEST CONDITIONS MIN TYP MAX UNIT RθJA Junction-to-ambient thermal resistance See Notes 4 and 7 90 RθJB Junction-to-board thermal resistance See Notes 5 and 7 44.5 °C/W RθJP Junction-to-pin thermal resistance See Notes 6 and 7 28 C/W NOTES: 4. Package mounted on an FR4 printed-circuit board with no heatsink. 5. Package mounted on a 24 in2, 4-layer FR4 printed-circuit board. 6. Package mounted in intimate contact with infinite heatsink. 7. All outputs with equal power |
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