TPIC5203

2CHANNEL INDEPENDENT GATEPROTECTED

POWER DMOS ARRAY

SLIS040 − SEPTEMBER 1994

Copyright

2−1

POST OFFICE BOX 655303

POST OFFICE BOX 1443

description

The TPIC5203 is a monolithic gate-protected

power

DMOS

array

that

consists

of

two

independent electrically isolated N-channel enhancement-mode DMOS transistors. Each transistor features

condition occurs. These zener diodes also provide up to 4000 V of ESD protection when tested using the

human-body model of a 100-pF capacitor in series with a 1.5-k

Ω resistor.

The TPIC5203 is offered in a standard eight-pin small-outline surface-mount (D) package and is characterized

for operation over the case temperature range of − 40

°C to 125°C.

schematic

D1

Z1

DRAIN1

GATE1

SOURCE1

Q1

7

8

D2

Z2

DRAIN2

GATE2

SOURCE2

Q2

3

4

2

GND

1

6

ZC1b

ZC1a

ZC2b

ZC2a

NOTE: For correct operation, no terminal pin may be taken below GND.

1

2

3

4

8

7

6

5

GND

SOURCE1

GATE2

DRAIN2

DRAIN1

GATE1

SOURCE2

NC

D PACKAGE

(TOP VIEW)

NC − No internal connection

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.