RESET_N

SPI/

Digital

BIAS

DIAG

VZ3

Z3

DGND2

SOMI

SCLK

TZ0

VDDIO

CS_N

SIMO

AGND

VA1

TEST4

NC

GND2

ZM2

Z2

VZ2

NC

NC

48

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

NC

NC

VZ0

Z0

ZM0

GND0

TEST

VCC5

AMX_OUT

AGND1

SQREF2

SQREF1

DGND1

IWD

VADC

TEST2

VA2

TEST3

GND1

ZM1

Z1

VZ1

NC

NC

NC

NC

ZM3

squib

GND3

squib

squib

squib

1

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

TPIC71004-Q1

www.ti.com

SLVSAT2

– FEBRUARY 2011

Table 2. Potential Deployment Settings for Maximum Firing Current

MAXIMUM AVERAGE FIRING

FIRING

VOLTAGE BETWEEN VZx AND

DWELL

VOLTAGE

Zx PINS TO ACHIEVE

DEPLOYMENT

35 V

30 V

2.6 A (for 1.75 A current setting)

0.7 ms

35 V

31 V

2.0 A (for 1.2 A current setting)

2.0 ms

(1)

The max firing current levels are set through device EEPROM setting

(2)

For programming desired dwell (firing) time

For the full version of this document, please contact msamktg@list.ti.com .

ORDERING INFORMATION

ORDERABLE PART

TOP-SIDE MARKING

NUMBER

–40°C to 125°C

HTSSOP

– DCA

Tape and reel

TPIC71004TDCAQ1

TPIC71004

TPIC71004TDCARQ1

(1)

“Pb-Free” is defined to be compliant with the current RoHS requirements for all 6 substances, including the requirement that lead not

exceed 0.1% by weight in homogeneous materials unless exempt. Where designed to be soldered at high temperatures, TI

"Pb-Free"

and

"RoHS Compliant" products are suitable for use in specified lead-free processes.

Functional Block Diagram

© 2011, Texas Instruments Incorporated

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