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74HC259-Q100 Folha de dados(PDF) 4 Page - NXP Semiconductors |
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74HC259-Q100 Folha de dados(HTML) 4 Page - NXP Semiconductors |
4 / 20 page 74HC_HCT259_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. Product data sheet Rev. 1 — 30 July 2012 4 of 20 NXP Semiconductors 74HC259-Q100; 74HCT259-Q100 8-bit addressable latch 5.2 Pin description 6. Functional description [1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; d = HIGH or LOW data one set-up time prior to the LOW-to-HIGH LE transition; q = lower case letter indicates the state of the referenced input one set-up time prior to the LOW-to-HIGH transition. Table 2. Pin description Symbol Pin Description A0, A1, A2 1, 2, 3 address input Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7 4, 5, 6, 7, 9, 10, 11, 12 latch output GND 8 ground (0 V) D 13 data input LE 14 latch enable input (active LOW) MR 15 conditional reset input (active LOW) VCC 16 supply voltage Table 3. Function table[1] Operating mode Input Output MR LE D A0 A1 A2 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Reset (clear) L H X X X X LLLLLLLL Demultiplexer (active HIGH 8-channel) decoder (when D = H) L L d L L L Q = d LLLLLLL L L d H L L LQ = d LLLLLL L L d L H L LLQ = d LLLLL L L d H H L LLLQ = d LLLL L L d L L H LLLLQ = d LLL L L d H L H LLLLLQ = d LL L L d L H H LLLLLLQ = d L L L d H H H LLLLLLLQ = d Memory (no action) H H X X X X q0 q1 q2 q3 q4 q5 q6 q7 Addressable latch H L d L L L Q = d q1 q2 q3 q4 q5 q6 q7 HL d HL L q0 Q=d q2 q3 q4 q5 q6 q7 HL d L HL q0 q1 Q=d q3 q4 q5 q6 q7 HL d HHL q0 q1 q2 Q=d q4 q5 q6 q7 H Ld LLH q0 q1 q2 q3 Q=d q5 q6 q7 HL d HL H q0 q1 q2 q3 q4 Q=d q6 q7 HL d L HH q0 q1 q2 q3 q4 q5 Q=d q7 HL d HHH q0 q1 q2 q3 q4 q5 q6 Q=d |
Nº de peça semelhante - 74HC259-Q100 |
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Descrição semelhante - 74HC259-Q100 |
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