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TSC2004IRTJT Folha de dados(PDF) 8 Page - Burr-Brown (TI) |
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TSC2004IRTJT Folha de dados(HTML) 8 Page - Burr-Brown (TI) |
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8 / 58 page  www.ti.com TIMING REQUIREMENTS for Figure 2: I 2C High-Speed Mode (f SCL = 1.7MHz) (1) TSC2004 SBAS408E – JUNE 2007 – REVISED MARCH 2008 All specifications typical at –40 °C to +85°C, SNSVDD = I/OVDD = +1.2V to +3.6V, unless otherwise noted. 2-WIRE HIGH-SPEED MODE PARAMETERS TEST CONDITIONS MIN MAX UNIT SNSVDD ≥ 1.6V 10 µs Reset low time(2) tWL(RESET) 1.2V ≤ SNSVDD < 1.6V 13 µs SCL clock frequency fSCL 1.7 MHz Hold time (repeated) START condition tHD, STA 160 ns Low period of SCL clock tLOW 320 ns High period of the SCL clock tHIGH 120 ns Setup time for a repeated START condition tSU, STA 160 ns Data hold time tHD, DAT 0 150 ns Data setup time tSU, DAT 10 ns Rise time of SCL signal tRCL Cb = total bus capacitance 20 80 ns Rise time of SDA signal tRDA Cb = total bus capacitance 20 160 ns Fall time of SCL signal tFCL Cb = total bus capacitance 20 80 ns Fall time of SDA signal tFDA Cb = total bus capacitance 20 160 ns Rise time of SCL signal after a repeated START tRCL1 Cb = total bus capacitance 20 160 ns condition and after an acknowledge bit Setup time for STOP condition tSU, STO 160 ns Capacitive load for each bus line Cb Cb = total capacitance of one bus line in pF 400 pF Pulse width of spike suppressed tSP 0 10 ns (1) All input signals are specified with tR = tF = 5ns (30% to 70% of VDD) and timed from a voltage level of (VIL + VIH)/2. (2) Refer to Figure 38. TIMING REQUIREMENTS for Figure 2: I 2C High-Speed Mode (f SCL = 3.4MHz) (1) All specifications typical at –40 °C to +85°C, SNSVDD = I/OVDD = +1.2V(2) to +3.6V, unless otherwise noted. 2-WIRE HIGH-SPEED MODE PARAMETERS TEST CONDITIONS MIN MAX UNIT SNSVDD ≥ 1.6V 10 µs Reset low time(3) tWL(RESET) 1.2V ≤ SNSVDD < 1.6V 13 µs SCL clock frequency fSCL 3.4 MHz Hold time (repeated) START condition tHD, STA 160 ns Low period of SCL clock tLOW 160 ns High period of the SCL clock tHIGH 60 ns Setup time for a repeated START condition tSU, STA 160 ns Data hold time tHD, DAT 0 70 ns Data setup time tSU, DAT 10 ns Rise time of SCL signal tRCL Cb = total bus capacitance 10 40 ns Rise time of SDA signal tRDA Cb = total bus capacitance 10 80 ns Fall time of SCL signal tFCL Cb = total bus capacitance 10 40 ns Fall time of SDA signal tFDA Cb = total bus capacitance 10 80 ns Rise time of SCL signal after a repeated START tRCL1 Cb = total bus capacitance 10 80 ns condition and after an acknowledge bit Setup time for STOP condition tSU, STO 160 ns Capacitive load for each bus line Cb Cb = total capacitance of one bus line in pF 100 pF Pulse width of spike suppressed tSP 0 10 ns (1) All input signals are specified with tR = tF = 5ns (30% to 70% of I/OVDD) and timed from a voltage level of (VIL + VIH)/2. (2) Because of the low supply voltage of 1.2V and the wide temperature range of –40 °C to +85°C, the I2C system devices may not reach the maximum specification of I2C High-Speed mode, and fSCL may not reach 3.4Mhz. (3) Refer to Figure 38. 8 Submit Documentation Feedback Copyright © 2007–2008, Texas Instruments Incorporated Product Folder Link(s): TSC2004 |
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