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FAN4274 Folha de dados(PDF) 9 Page - Fairchild Semiconductor |
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FAN4274 Folha de dados(HTML) 9 Page - Fairchild Semiconductor |
9 / 13 page © 2004 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN4174/FAN4274 • Rev. 1.0.8 9 Layout Considerations General layout and supply bypassing play major roles in high-frequency performance. Fairchild evaluation boards help guide high-frequency layout and aid in device testing and characterization. Follow the steps below as a basis for high-frequency layout: 1. Include 6.8μF and 0.01μF ceramic capacitors. 2. Place the 6.8μF capacitor within 0.75 inches of the power pin. 3. Place the 0.01μF capacitor within 0.1 inches of the power pin. 4. Remove the ground plane under and around the part, especially near the input and output pins, to reduce parasitic capacitance. Minimize all trace lengths to reduce series inductances. Refer to the evaluation board layouts shown in Figures 28-31 for more information. When evaluating only one channel, complete the following on the unused channel: 1. Ground the non-inverting input. 2. Short the output to the inverting input. Evaluation Board Information The following evaluation boards are available to aid in the testing and layout of this device: Evaluation Board Description Products KEB002 Single Channel, Dual Supply, 5 and 6-Lead SOT23 FAN4174IS5X KEB010 Dual Channel, Dual Supply 8-Lead MSOP FAN4274IMU8X Evaluation board schematics are shown in Figure 25 and Figure 26; layouts are shown in Figures 28-31. Figure 25. FAN4174 Evaluation Board Schematic (KEV002) Figure 26. FAN4274 Evaluation Board Schematic (KEB010) |
Nº de peça semelhante - FAN4274_12 |
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Descrição semelhante - FAN4274_12 |
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