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74AUP1G59FHX Folha de dados(PDF) 2 Page - Fairchild Semiconductor |
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74AUP1G59FHX Folha de dados(HTML) 2 Page - Fairchild Semiconductor |
2 / 10 page © 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com 74AUP1G59 • Rev. 1.0.4 2 Pin Configurations 1 B 2 GND 3 6 5 4 A C VCC Y Figure 1. MicroPak™ (Top Through View) Pin Definitions Pin # Name Description 1 B Data Input 2 GND Ground 3 A Data Input 4 Y Output (Open Drain) 5 VCC Supply Voltage 6 C Data Input Function Table Inputs Y=Output C B A L L L L L L H H (1) L H L L L H H H (1) H L L H (1) H L H H (1) H H L L H H H L H = HIGH Logic Level L = LOW Logic Level Note: 1. High impedance output state, open drain. Function Selection Table 2-Input Logic Function Connection Configuration 2-Input AND with Inverted Input Figure 3, Figure 4 2-Input NAND Figure 2 2-Input NAND with Both Inputs Inverted Figure 5 2-Input OR Figure 5 2-Input OR Both Inputs Inverted Figure 2 2-Input NOR with Inverted Input Figure 3, Figure 4 2-Input XNOR Figure 6 Inverter Figure 7 Buffer Figure 8 |
Nº de peça semelhante - 74AUP1G59FHX |
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Descrição semelhante - 74AUP1G59FHX |
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