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FM24CL64B-DGTR Folha de dados(PDF) 2 Page - Cypress Semiconductor

Nome de Peças FM24CL64B-DGTR
Descrição Electrónicos  64Kb Serial 3V F-RAM Memory
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Fabricante Electrônico  CYPRESS [Cypress Semiconductor]
Página de início  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

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FM24CL64B
Rev. 3.0
Jan. 2012
Page 2 of 13
Address
Latch
1,024 x 64
FRAM Array
Data Latch
8
SDA
Counter
Serial to Parallel
Converter
Control Logic
SCL
WP
A0-A2
Figure 1. FM24CL64B Block Diagram
Pin Description
Pin Name
Type
Pin Description
A0-A2
Input
Address 0-2. These pins are used to select one of up to 8 devices of the same type on
the same two-wire bus. To select the device, the address value on the three pins must
match the corresponding bits contained in the device address. The address pins are
pulled down internally.
SDA
I/O
Serial Data Address. This is a bi-directional line for the two-wire interface. It is
open-drain and is intended to be wire-OR’d with other devices on the two-wire bus.
The input buffer incorporates a Schmitt trigger for noise immunity and the output
driver includes slope control for falling edges. A pull-up resistor is required.
SCL
Input
Serial Clock. The serial clock line for the two-wire interface. Data is clocked out of
the part on the falling edge, and in on the rising edge. The SCL input also
incorporates a Schmitt trigger input for noise immunity.
WP
Input
Write Protect. When WP is high, addresses in the entire memory map will be write-
protected. When WP is low, all addresses may be written. This pin is pulled down
internally.
VDD
Supply
Supply Voltage: 2.7V to 3.6V
VSS
Supply
Ground


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