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AD1849K Folha de dados(PDF) 9 Page - Analog Devices |
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AD1849K Folha de dados(HTML) 9 Page - Analog Devices |
9 / 28 page AD1849K REV. 0 –9– On input, 8-bit companded data is expanded to an internal linear representation, according to whether µ-law or A-law was specified in the Codec’s internal registers. Note that when µ-law compressed data is expanded to a linear format, it requires 14 bits. A-law data expanded requires 13 bits, see Figure 1. 3/2 2/1 15 0 15 0 MSB MSB 0 0 0 / 0 0 15 0 MSB DAC INPUT EXPANSION COMPRESSED INPUT DATA 3/2 2/1 LSB LSB 8 7 LSB Figure 1. A-Law or µ-Law Expansion When 8-bit companding is specified, the ADCs’ linear output is compressed to the format specified prior to output. See Figure 2. Note that all format conversions take place at input or output. Internally, the AD1849K always uses 16-bit linear PCM representations to maintain maximum precision. LSB 3/2 2/1 15 0 15 0 MSB MSB 0 0 0 0 0 0 0 0 15 0 MSB ADC OUTPUT TRUNCATION COMPRESSION LSB 8 7 LSB Figure 2. A-Law or µ-Law Compression Power Supplies and Voltage Reference The AD1849K operates from +5 V power supplies. Independent analog and digital supplies are recommended for optimal performance, though excellent results can be obtained in single supply systems. A voltage reference is included on the Codec and its 2.25 V buffered output is available on an external pin (CMOUT). The CMOUT output can be used for biasing op amps used in dc coupling. The internal reference is externally bypassed to analog ground at the VREF pin. Note that VREF should only be connected to its bypass capacitors. Autocalibration The AD1849K supports an autocalibration sequence to eliminate DAC and ADC offsets. The autocalibration sequence is initiated in the transition from Control Mode to Data Mode, regardless of the state of the AC bit. The user should specify that analog outputs be muted to prevent undesired outputs. Monitor mix will be automatically disabled by the Codec. During the autocalibration sequence, the serial data output from the ADCs is meaningless and the ADI bit is asserted. Serial data inputs to the DACs are ignored. Even if the user specified the muting of all analog outputs, near the end of the autocalibration sequence, dc analog outputs very close to CMOUT will be produced at the line outputs and mono speaker output. An autocalibration sequence is also performed when the AD1849K leaves the reset state (i.e., RESET goes HI). The RESET pin should be held LO for 50 ms after power up or after leaving power-down mode to delay the onset of the autocalibration sequence until after the voltage reference has settled. Loopback Digital and analog loopback modes are supported for device and system testing. The monitor mix datapath is always available for loopback test purposes. Additional loopback tests are enabled by setting the ENL bit (Control Word Bit 33) to a “1.” Analog loopback mode D-A-D is enabled by setting the ADL bit (Control Word Bit 32) to a “1” when ENL is a “1.” In this mode, the DACs’ analog outputs are re-input to the PGAs prior to the ADCs, allowing digital inputs to be compared to digital outputs. The monitor mix will be automatically disabled by the Codec during D-A-D loopback. The analog outputs can be individually attenuated, and the analog inputs are internally disconnected. Note that muting the line 0 output mutes the looped-back signal in this mode. Digital loopback mode D-D is enabled by resetting the ADL bit (Control Word Bit 32) to a “0” when ENL is a “1.” In this mode, the control and data bit pattern presented on the SDRX pin is echoed on the SDTX pin with a two frame delay, allowing the host controller to verify the integrity of the serial interface starting on the third frame after D-D loopback is enabled. During digital loopback mode, the output DACs are operational. |
Nº de peça semelhante - AD1849K |
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Descrição semelhante - AD1849K |
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