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AD1955YRS Folha de dados(PDF) 9 Page - Analog Devices

Nome de Peças AD1955YRS
Descrição Electrónicos  High Performance Multibit DAC with SACD Playback
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Fabricante Electrônico  AD [Analog Devices]
Página de início  http://www.analog.com
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AD1955YRS Folha de dados(HTML) 9 Page - Analog Devices

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AD1955
Rev. PrF
-9-
PRELIMINARY TECHNICAL DATA
Audio Outputs
The AD1955 audio outputs sink a current proportional to the input signal, superimposed on a steady state current. The current-to-
voltage (I/V) converters used need to be able to supply this steady state current as well as the signal current or a resistor or current
source can be used to a positive voltage to null this current to center the range of the I/V converters. Active I/V converters should be
used, referenced to FILTR, and should hold the DAC outputs at this voltage level. Passive I/V conversion should not be used as the
DAC performance will be seriously degraded.
Serial Control Port
The AD1955 has an SPI compatible control port to permit programming the internal control registers. The SPI control port is a three
wire serial port. Its format is similar to the Motorola SPI format except that the input data word is 16-bits wide. The serial bit clock
may be completely asynchronous to the sample rate of the DAC. The following figure shows the format of the SPI signal. Note that
the CCLK may be continuous or a 16-clock burst.
SPI REGISTER DEFINITIONS
Table 1: DAC Control Register 0
Bit 13: 12
Bit 11: 10
Bit 9:8
Bit 7:6
Bit 5: 4
Bit 3: 2
Bit 1: 0
Data format
Output Format
PCM Sample Rate
De-Emphasis
Curve Select
PCM/ EF Serial
Data Format
PCM/ EF Serial
Data Width
SPI Register
Address
00 : PCM
01 : Ext. DF
10 : SACD Slave
11 : SACD
Master
00 : Stereo
01 : Not
Allowed
10 : Mono Left
11 : Mono Right
00 : 48kHz
01 : 96kHz
10 : 192kHz
11 : Rsvd
00 : None
01 : 44.1kHz
10 : 32kHz
11 : 48kHz
00 : I2S
01 : Right-Just
10 : DSP
11 : LEFT-Just
00 : 24Bits
01 : 20Bits
10 : 18Bits
11 : 16Bits
00
Bit 15
Bit 14
Power Down
Mute
0 : Operation
1 : Powered
Down
0 : Not Muted
1 : Muted
Note: 0 = Default Setting
Table 2: DAC Control Register 1
Bits 10:9
Bit 8
Bit 7
Bit 6
Bit 5:4
Bit 3
Bit 2
Bit 1: 0
MCLK
Mode
Zero Flag
Polarity
SACD Bit Rate
SACD Mode
SACD Phase
Select
SACD Bit
Inversion
SACD BCLK to
MCLK Phase
SPI Register
Address
00 : 256fs
01 : 512fs
10 : 768fs
11 : 384fs
0 : Active high
1: Active low
0 : 8fs / 64fs
1 : 4fs / 128fs
0 : Normal
1 : Phase Mode
00 : Phase 0
01 : Phase 1
10 : Phase 2
11 : Phase 3
0 : Normal
1 : Inverted
0 : Rising edge
1 : Falling edge
01
Note: 0 = Default Setting
Table 3: DAC Volume Registers
Note: Default = full volume
Bit 15: 2
Bit 1: 0
Volume
SPI Register Address
14bit, Unsigned
10 = Left Volume
14bit, Unsigned
11 = Right Volume
D0
D15
D14
CLATCH
CCLK
CDATA


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