AD5533ABC-1 datasheet(4/16 Pages) AD

Nome de Peças	AD5533ABC-1

Descrição Electrónicos	32-Channel, 14-Bit Voltage-Output DAC

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Fabricante Electrônico	AD [Analog Devices]

Página de início	http://www.analog.com

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4 / 16 page

REV. 0

AD5532

–4–

TIMING CHARACTERISTICS

PARALLEL INTERFACE

Limit at TMIN, TMAX

Parameter

1, 2

(A Version)

Unit

Conditions/Comments

t1

0

ns min

CS to WR Setup Time

t2

0

ns min

CS to WR Hold Time

t3

50

ns min

CS Pulsewidth Low

t4

50

ns min

WR Pulsewidth Low

t5

20

ns min

A4–A0, CAL, OFFS_SEL to

WR Setup Time

t6

0

ns min

A4–A0, CAL, OFFS_SEL to

WR Hold Time

NOTES

1See Interface Timing Diagram.

2Guaranteed by design and characterization, not production tested.

Specifications subject to change without notice.

SERIAL INTERFACE

Limit at TMIN, TMAX

Parameter

1, 2

(A Version)

Unit

Conditions/Comments

fCLKIN

3

14

MHz max

SCLK Frequency

t1

28

ns min

SCLK High Pulsewidth

t2

28

ns min

SCLK Low Pulsewidth

t3

10

ns min

SYNC Falling Edge to SCLK Falling Edge Setup Time

t4

50

ns min

SYNC Low Time

t5

10

ns min

DIN Setup Time

t6

5

ns min

DIN Hold Time

t7

5

ns min

SYNC Falling Edge to SCLK Rising Edge Setup Time

t8

4

20

ns max

SCLK Rising Edge to DOUT Valid

t9

4

60

ns max

SCLK Falling Edge to DOUT High Impedance

t10

400

ns min

10th SCLK Falling Edge to

SYNC Falling Edge for Readback

t11

400

ns min

24th SCLK Falling Edge to

SYNC Falling Edge for DAC Mode Write

NOTES

1See Serial Interface Timing Diagrams.

2Guaranteed by design and characterization, not production tested.

3In SHA mode the maximum SCLK frequency is 20 MHz and the minimum pulsewidth is 20 ns.

4These numbers are measured with the load circuit of Figure 2.

Specifications subject to change without notice.

PARALLEL INTERFACE TIMING DIAGRAMS

CS

WR

A4–A0, CAL,

OFFS SEL

Figure 1. Parallel Write (SHA Mode Only)

IOL

200 A

IOH

200 A

CL

50pF

TO

OUTPUT

1.6V

Figure 2. Load Circuit for DOUT Timing Specifications

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