AD6458

–11–

REV. 0

MXP

275

Ω

275

Ω

25k

Ω

160k

Ω

MXM

VPOS

FROM

MIXER

CORE

MXOP

330

Ω

Figure 32. Mixer Output Port

IF Amplifier

Most of the gain in the AD6458 resides in the IF amplifier strip,

which comprises two stages. Both are fully differential and each

has a gain span of 26 dB for the AGC voltage range of 0.2 V to

2.25 V. Thus, in conjunction with the variable gain of the mixer,

the total gain span is 76 dB. The overall IF gain varies from –9

dB to 48 dB for the nominal AGC voltage of 0.2 V to 2.25 V.

The IF input is differential at IFIP and IFIM. Figure 33 shows a

simplified schematic of the IF interface modeled as parallel RC

network.

The IF’s small-signal bandwidth is approximately 50 MHz from

IFIP and IFIM through the demodulator.

IFHI

IFLO

Figure 33. IF Amplifier Port Modeled as a Parallel RC

Network

Gain Scaling

The AD6458’s overall gain, expressed in decibels, is linear with

supply voltage. The gain of all stages changes simultaneously.

The AD6458’s gain scaling is also temperature compensated.

The GAIN pin of the AD6458 is an input driven by an external

low impedance voltage source, normally a DAC, under the

control of radio’s digital processor.

The gain-control scaling is directly proportional to the reference

voltage applied to the pin GREF and is independent of the

power supply voltage. When this input is set to the nominal

value of 1.2 V, the scale is nominally 27 mV/dB (37 dB/V).

Under these conditions, 76 dB of gain range (mixer plus IF)

final centering of this 2.05 V range depends on the insertion

losses of the IF filters used.

provided, for example, by a AD1580 (1.21 V) voltage reference.

AD6458

IRXP

IRXN

QRXP

QRXN

GREF

GAIN

FREF

AD6421

100pF

100pF

100pF

100pF

0.1µF

160

Ω

1nF

VCTCXO

IRXP

IRXN

QRXP

QRXN

BREFOUT

BREFCAP

AGC DAC

AFC DAC

Figure 34. Interfacing the AD6458 to the AD6421

Baseband Converter

When using the Analog Devices AD7013 (IS54, TETRA and

satellite receiver applications) and AD7015 or AD6421 (GSM,

DCS1800, PCS1900) baseband converters, the external ref-

erence may also be provided by the reference output of the

baseband converters. The interface between the AD6458 and

the AD6421 baseband converter is shown in Figure 34. The

auxiliary DAC in the AD6421 can be used to generate the AGC

voltage. Since it uses the same reference voltage, the numerical

input to this DAC provides an accurate RSSI value in digital

form, no longer requiring the reference voltage to have high

absolute accuracy.

I/Q Demodulators

Both demodulators (I and Q) receive their inputs internally

from the IF amplifiers. Each demodulator comprises a full-wave

synchronous detector followed by an 8 MHz, two-pole low-pass

filter, producing differential outputs at pins IRXP and IRXN,

and QRXP and QRXN. Using the I and Q demodulators for IFs

above 50 MHz is precluded by the 5 MHz to 50 MHz range of

the PLL used in the demodulator section.

The I and Q outputs are differential and can swing up to

2.2 V p-p at the low supply voltage of 3.0 V. They are nominally

centered at 1.5 V independently of power supply. They can

therefore directly drive the RX ADCs in the AD6421 baseband

converter, which require an amplitude of 1.23 V to fully load

them when driven by a differential signal. The conversion gain

of the I and Q demodulators is 17 dB.

For IFs of less than 8 MHz, the on-chip low-pass filters (8 MHz

cutoff) do not adequately attenuate the IF or feedthrough prod-

ucts; the maximum input voltage must thus be limited to allow

sufficient headroom at the I and Q outputs, not only for the de-

sired baseband signal but also the unattenuated higher order

demodulation products. These products can be removed by an

external low-pass filter. A simple 1-pole RC filter, with its cor-

ner above the modulation bandwidth, is sufficient to attenuate

undesired outputs. The design of the RC filter is eased by the

4.7 k

Ω resistor integrated at each I and Q output pin.