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AD6622S Folha de dados(PDF) 11 Page - Analog Devices |
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AD6622S Folha de dados(HTML) 11 Page - Analog Devices |
11 / 28 page AD6622 –11– REV. 0 The serial data frame sync output, SDFS, is pulsed high for one SCLK cycle at the input sample rate. The input sample rate is determined by the master clock divided by channel interpolation factor. If the SCLK rate is not an integer multiple of the input sample rate, the SDFS will continually adjust the period by one SCLK cycle in order to keep the average SDFS rate equal to the input sample rate. When the channel is in sleep mode, SDFS is held low. The first SDFS is delayed by the channel reset latency after the Channel Reset is removed. The channel reset latency varies dependent on channel configuration. The serial data input, SDIN, accepts 32-bit words as channel input data. The 32-bit word is interpreted as two 16 bit two’s complement quadrature words, I followed by Q, MSB first. The first bit is shifted into the serial port starting on the second rising edge of SCLK after SDFS goes high, as shown by the timing diagram below. CLK SCLK SDFS SDI CLKn DATAn tDSCLK tDSDFS tDSDFS tSSI tHSI Figure 10. Serial Port Switching Characteristics As an example of the serial port operation, consider a CLK fre- quency of 62.208 MSPS and a channel interpolation of 2560. In that case, the input sample rate is 24.3 kSPS (62.208 MSPS/ 2560), which is also the SDFS rate. Substituting, fSCLK ≥ 32 × fSDFS into the equation below and solving for SCLKDIVIDER, we find the maximum value for SCLKDIVIDER according to Equation 2. SCLK f DIVIDER SDFS ≤ × f CLK 64 1 – (2) Evaluating this equation for our example, SCLKDIVIDER must be less than or equal to 39. Since the SCLKDIVIDER channel regis- ter is a 5-bit unsigned number it can only range from 0 to 31. Any value in that range will be valid for this example, but if it is important that the SDFS period is constant, then there is another restriction. For regular frames, the ratio fSCLK/fSDFS must be equal to an integer of 32 or larger. For this example, constant SDFS periods can only be achieved with an SCLK divider of 19. In conclusion, the SDFS rate is determined by the AD6622 master clock rate and the interpolation rate of the channel. The SDFS rate is equal to the channel input rate. The channel interpola- tion is equal to RCF interpolation times CIC5 interpolation, times CIC2 interpolation LL L L RCF CIC CIC =× × 52 (3) The SCLK rate is determined by the AD6622 master clock rate and SCLKDIVIDER. The SCLK is a divided version of the AD6622 master CLK. The SCLK divide ratio is determined by SCLKDIVIDER as shown in Equation 2. The SCLK must be fast enough to input 32 bits of data prior to the next SDFS. Extra SCLKs are ignored by the serial port. PROGRAMMABLE INTERPOLATING RAM COEFFICIENT FILTER (RCF) Each channel has a fully independent RAM Coefficient Filter (RCF). The RCF accepts data from the serial port, filters it, and passes the result to the CIC filter. The RCF implements a FIR filter with optional interpolation. The FIR filter can produce impulse responses up to 128 output samples long. The FIR response may be interpolated up to a factor of 128, although the best filter performance is usually achieved if the RCF inter- polation factor is confined to 8 or below. FIR Filter Implementation The RCF accepts quadrature samples from the serial port with a fixed point resolution of 16 bits each, for I and Q. SERIAL PORT DATA MEM RCF RCF COARSE SCALE COEFFICIENT MEM IQ TO CIC FILTER SDFS SCLK SDIN 16,16 ACCUMULATOR 16,16 16,16 Figure 11. RCF Block Diagram The AD6622 RCF realizes a sum-of-products filter using a poly- phase implementation. This mode is equivalent to an interpola- tor followed by a FIR filter running at the interpolated rate. In Figure 12, the interpolating block increases the rate by the RCF interpolation factor (LRCF) by inserting LRCF-1 zero valued samples between every input sample. The next block is a filter with a finite impulse response length (NRCF) and an impulse response of h[n], where n is an integer from 0 to NRCF-1. LRCF fIN a b c fIN LRCF NRCF TAP FIR FILTER h[n] fIN LRCF Figure 12. RCF Interpolation The difference equation for Figure 12 is written below, where h[n] is the RCF impulse response, b[n] is the interpolated input sample sequence at point “b” in Figure 12, and c[n] is the out- put sample sequence at point “c” in the Figure 12. cn hk n b n k NRCF [] [ ] [] =− ∑ × = − 0 1 (4) This difference equation can be described by the transfer func- tion from point “b” to “c” as shown Equation 5. Hz h n z bc n N n RCF () [ ] = ∑ × = − − 0 1 (5) The actual implementation of this filter uses a polyphase decomposition to skip the multiply-accumulates when b[n] is zero. Compared to the diagram above, this implementation has the benefits of reducing by a factor of LRCF both the time needed to calculate an output and the required data memory (DMEM). The price of these benefits is that the user must place the coefficients into the coefficient memory (CMEM) indexed by the interpo- lation phase. The process of selecting the coefficients and placing them into the CMEM is broken into three steps shown below. |
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