AD7394/AD7395

–6–

REV. 0

PIN FUNCTION DESCRIPTIONS

Pin

No.

Name

Function

1

AGND

Analog Ground.

DAC A Voltage Output.

4

DGND

Digital Ground. Should be tied to analog GND.

5

CS

Chip Select, active low input. Disables shift register loading when high. Does not effect

LDA or LDB operation.

6

CLK

Clock input, positive edge clocks data into shift register, MSB data bit first.

7

SDI

Serial Data Input, input data loads directly into the shift register.

8

LDA

Load DAC register strobe, level sensitive active low. Transfers shift register data to DAC A register. Asyn-

chronous active low input. See Control Logic Truth Table for operation.

9

RS

Resets DAC register to zero condition or half-scale, depending on MSB pin logic level. Asynchronous active

low input.

10

LDB

Load DAC register strobe, level-sensitive active low. Transfers shift register data to DAC B register. Asyn-

chronous active low input. See Control Logic Truth Table for operation.

11

MSB

12

SHDN

data can be loaded into the shift register and DAC register during shutdown. When device is powered up the

most recent data loaded into the DAC register will control the DAC output.

13

Positive power supply input. Specified range of operation +2.7 V to +5.5 V

14

DAC B Voltage Output.

PIN CONFIGURATIONS

TOP VIEW

(Not to Scale)

14

13

12

11

10

9

8

1

2

3

4

5

6

7

AGND

DGND

CS

CLK

SDI

SHDN

MSB

LDB

RS

LDA

AD7394

AD7395