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AD7750AN Folha de dados(PDF) 10 Page - Analog Devices |
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AD7750AN Folha de dados(HTML) 10 Page - Analog Devices |
10 / 16 page AD7750 –10– REV. 0 Maximum Output Frequencies Table II shows the maximum output frequencies of FOUT and F1, F2 for the various operating modes of the AD7750. The table shows the maximum output frequencies for dc and ac input signals on V1 and V2. When an ac signal (sinusoidal) is applied to V1 and V2 the AD7750 produces an output frequency which is proportional to the product of the rms value of these inputs. If two ac signals with peak differential values of V1MAX and V2MAX are applied to Channels 1 and 2, respectively, then the output frequency is proportional to V1MAX/sqrt(2) × V 2MAX/ sqrt(2) = (V1MAX × V 2MAX)/2. If V1MAX and V2MAX are also the maximum dc input voltages then the maximum output frequen- cies for ac signals will always be half that of dc input signals. Example calculation of F1, F2 max for Mode 2 and Gain = 1. The maximum input voltage (dc) on Channel 1 is 2 V (V1+ = +1 V, V1– = –1 V)—see Analog Inputs section. The maximum input voltage on Channel 2 is 1 V. Using the transfer function: k = (1.32 × V 1 × V 2 × Gain)/V REF 2 k = 0.4224 F1, F2 = k.6.8 Hz = 2.9 Hz FUNCTIONAL DESCRIPTION The AD7750 combines two analog-to-digital converters, a digi- tal multiplier, digital filters and a digital-to-frequency (DTF) converter onto one low cost integrated circuit. The AD7750 is fabricated on a double poly CMOS process (0.6 µ) and retains its high accuracy by performing all multiplications and manipu- lations in the digital domain. The schematic in Figure 15 shows an equivalent circuit for the AD7750 signal processing chain. The first thing to notice is that the analog signals are first con- verted to digital signals by the two second-order sigma-delta modulators. All subsequent signal processing is carried out in the digital domain. The main source of errors in an application is therefore in the analog-to-digital conversion process. For this reason great care must be taken when interfacing the analog inputs of the AD7750 to the transducer. This is discussed in the Applications section. HPF in Channel 1 To remove any dc offset that may be present at the output modulator 1, a user selectable high-pass IIR filter (Pin ACDC) can be introduced into the signal path. This HPF is necessary when carrying out power measurements. However, this HPF has an associated phase lead given by 90 °–tan–1(f/2.25). Figure 16 shows the transfer function of the HPF in Channel 1. The Phase lead is 2.58 ° at 50 Hz. In order to equalize the phase difference between the two channels a fixed time delay is intro- duced. The time delay is set at 143 µs, which is equivalent to a phase lag of –2.58 ° at 50 Hz. Thus the cumulative phase shift through Channel 1 is 0 °. Because the time delay is fixed, external phase compensation circuitry will be required if the line frequency differs from 50 Hz. For example with a line frequency of 60 Hz the phase lead due to the HPF is 2.148 ° and the phase lag due to the fixed time delay is 3.1 °. This means there is a net phase lag in Chan- nel 1 of 0.952 °. This phase lag in Channel 1 can be compen- sated for by using a phase lag compensation circuit like the one shown in Figure 17. The phase lag compensation is placed on Channel 2 (voltage channel) to equalize the channels. The antialiasing filter associated with Channel 1 (see Applications section) produces a phase lag of 0.6 ° at 50 Hz; therefore, to equalize the channels, a net phase lag of (0.6 ° + 0.952°) 1.552° should be in place on Channel 2. The gain trim resistor VR1 (100 Ω) produces a phase lag variation of 1.4° to 1.5° with VR2 = 0 Ω. VR2 can add an additional 0.1° phase lag (VR2 = 200 Ω). V2 (+) FOUR QUADRANT MULTIPLICATION (SIGN AND MAGNITUDE) TWO QUADRANT MULTIPLICATION ( MAGNITUDE ONLY) (1.32 V1 V2 GAIN) VREF 2 K = V2(–) 0 V2(–) V2 (+) k FMAX (+) FMAX + k FMAX (+) FMAX – k FMAX (–) k FMAX (+) FMAX + k FMAX (+) FMAX _ k FMAX (–) k FMAX (+) k FMAX (+) V1(–) V1(+) V1(–) V1(+) Figure 14. Transfer Functions (Four and Two Quadrant Multiplication) |
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