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AD7856 Folha de dados(PDF) 5 Page - Analog Devices

Nome de Peças AD7856
Descrição Electrónicos  5 V Single Supply, 8-Channel 14-Bit 285 kSPS Sampling ADC
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Fabricante Electrônico  AD [Analog Devices]
Página de início  http://www.analog.com
Logo AD - Analog Devices

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AD7856
–5–
REV. A
TYPICAL TIMING DIAGRAMS
Figures 2 and 3 show typical read and write timing diagrams for
serial Interface Mode 2. The reading and writing occurs after
conversion in Figure 2, and during conversion in Figure 3. To
attain the maximum sample rate of 285 kHz, reading and writ-
ing must be performed during conversion as in Figure 3. At
least 330 ns acquisition time must be allowed (the time from
the falling edge of BUSY to the next rising edge of
CONVST)
before the next conversion begins to ensure that the part is
settled to the 14-bit level. If the user does not want to provide
the
CONVST signal, the conversion can be initiated in software
by writing to the control register.
tCONVERT = 3.5 s MAX, 5.25 s MAX FOR K VERSION
t1 = 100ns MIN, t4 = 30/50ns MAX A/K, t7 = 30/40ns MIN A/K
DB15
SYNC (I/P)
SCLK (I/P)
t3
BUSY (O/P)
CONVST (I/P)
tCONVERT
1
5
616
DOUT (O/P)
DB0
DB11
DIN (I/P)
DB15
DB0
THREE-
STATE
DB11
THREE-STATE
t1
t2
t4
t6
t6
t9
t11
t12
t8
t7
t10
Figure 2. Timing Diagram for Interface Mode 2 (Reading/Writing After Conversion)
DB15
SYNC (I/P)
SCLK (I/P)
t3
BUSY (O/P)
CONVST (I/P)
tCONVERT
1
5
616
DOUT (O/P)
DB0
DB11
DIN (I/P)
DB15
DB0
THREE-
STATE
DB11
THREE-STATE
t1
t2
t4
t6
t6
t9
t11
t12
t8
t7
t10
tCONVERT = 3.5 s MAX, 5.25 s MAX FOR K VERSION
t1 = 100ns MIN, t4 = 30/50ns MAX A/K, t7 = 30/40ns MIN A/K
Figure 3. Timing Diagram for Interface Mode 2 (Reading/Writing During Conversion)
TO OUTPUT
PIN
CL
100pF
IOL
1.6mA
200 A
+2.1V
IOL
Figure 1. Load Circuit for Digital Output Timing
Specifications


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