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AD7866ARU Folha de dados(PDF) 2 Page - Analog Devices

Nome de Peças AD7866ARU
Descrição Electrónicos  Dual 1 MSPS, 12-Bit, 2-Channel SAR ADC with Serial Interface
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Fabricante Electrônico  AD [Analog Devices]
Página de início  http://www.analog.com
Logo AD - Analog Devices

AD7866ARU Folha de dados(HTML) 2 Page - Analog Devices

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REV. 0
–2–
AD7866–SPECIFICATIONS1
(TA = TMIN to TMAX, VDD = 2.7 V to 5.25 V, VDRIVE = 2.7 V to 5.25 V, Reference = 2.5 V
External on DCAPA and DCAPB, fSCLK = 20 MHz, unless otherwise noted.)
Parameter
A Version
1
B Version
1
Unit
Test Conditions/Comments
DYNAMIC PERFORMANCE
Signal to Noise + Distortion (SINAD)
2
68
68
dB min
fIN = 300 kHz Sine Wave, fS = 1 MSPS
Total Harmonic Distortion (THD)2
–75
–75
dB max
fIN = 300 kHz Sine Wave, fS = 1 MSPS
Peak Harmonic or Spurious Noise (SFDR)
2
–76
–76
dB max
fIN = 300 kHz Sine Wave, fS = 1 MSPS
Intermodulation Distortion (IMD)
2
Second Order Terms
–88
–88
dB typ
Third Order Terms
–88
–88
dB typ
Channel to Channel Isolation
–88
–88
dB typ
SAMPLE AND HOLD
Aperture Delay
3
10
10
ns max
Aperture Jitter
3
50
50
ps typ
Aperture Delay Matching3
200
200
ps max
Full Power Bandwidth
12
12
MHz typ
@ 3 dB
2
2
MHz typ
@ 0.1 dB
DC ACCURACY
Resolution
12
12
Bits
Integral Nonlinearity
±1.5
±1LSB max
B Grade, 0 V to VREF range only;
±0.5 LSB typ
± 1.5
LSB max
0 V to 2
× VREF range; ± 0.5 LSB typ
Differential Nonlinearity
–0.95/+1.25
–0.95/+1.25
LSB max
Guaranteed No Missed Codes to 12 Bits
0 V to VREF Input Range
Straight Binary Output Coding
Offset Error
±8
±8LSB max
Offset Error Match
±1.2
±1.2
LSB typ
Gain Error
±2.5
±2.5
LSB max
Gain Error Match
±0.2
±0.2
LSB typ
2
× VREF Input Range
–VREF to +VREF Biased about VREF with
Positive Gain Error
±2.5
±2.5
LSB max
Two’s Complement Output Coding
Zero Code Error
±8
±8LSB max
Zero Code Error Match
±0.2
±0.2
LSB typ
Negative Gain Error
±2.5
±2.5
LSB max
ANALOG INPUT
Input Voltage Ranges
0 to VREF
0 to VREF
V
RANGE Pin Low upon
CS Falling Edge
0 to 2
× V
REF 0 to 2
× V
REF
V
RANGE Pin High upon
CS Falling Edge
DC Leakage Current
±500
±500
nA max
Input Capacitance
30
30
pF typ
When in Track
10
10
pF typ
When in Hold
REFERENCE INPUT/OUTPUT
Reference Input Voltage
2.5
2.5
V
±1% for Specified Performance
Reference Input Voltage Range
4
2/3
2/3
V min/V max REF SELECT Pin Tied High
DC Leakage Current
±30
±30
µA max
VREF Pin;
±160
±160
µA max
DCAPA, DCAPB Pins;
Input Capacitance
20
20
pF typ
Reference Output Voltage
5
2.45/2.55
2.45/2.55
V min/V max
VREF Output Impedance
6
25
25
Ω typ
VDD = 5 V
45
45
Ω typ
VDD = 3 V
Reference Temperature Coefficient
50
50
ppm/
°C typ
REF OUT Error (TMIN to TMAX)
±15
±15
mV typ
LOGIC INPUTS
Input High Voltage, VINH
0.7 VDRIVE
0.7 VDRIVE
V min
Input Low Voltage, VINL
0.3 VDRIVE
0.3 VDRIVE
V max
Input Current, IIN
±1
±1
µA max
Typically 15 nA, VIN = 0 V or VDRIVE
Input Capacitance, CIN
3
10
10
pF max
LOGIC OUTPUTS
Output High Voltage, VOH
VDRIVE – 0.2 VDRIVE – 0.2
V min
ISOURCE = 200
µA
Output Low Voltage, VOL
0.4
0.4
V max
ISINK = 200
µA
Floating-State Leakage Current
±1
±1
µA max
VDD = 2.7 V to 5.25 V
Floating-State Output Capacitance
3
10
10
pF max
Output Coding
Straight (Natural) Binary
Selectable with Either Input Range
Two’s Complement


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