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AD8313-EVAL Folha de dados(PDF) 10 Page - Analog Devices |
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AD8313-EVAL Folha de dados(HTML) 10 Page - Analog Devices |
10 / 16 page AD8313 –10– REV. B Setpoint Interface, VSET The setpoint interface is shown in Figure 26. The voltage VSET is divided by a factor of three in a resistive attenuator of total resistance 18 k Ω. The signal is converted to a current by the action of the op amp and the resistor R3 (1.5 k Ω), which bal- ances the current generated by the summed output of the nine detector cells at the input to the previous cell. The logarithmic slope is nominally 3 × 4.0 µA/dB × 1.5 kΩ ≈ 18 mV/dB. VSET VPOS R1 12k COMM FDBK TO O/P STAGE 1 R2 6k R3 1.5k 25 A 25 A 8 6 LP Figure 26. Setpoint Interface Circuitry APPLICATIONS Basic Connections for Log (RSSI) Mode Figure 27 shows the AD8313 connected in its basic measure- ment mode. A power supply of +2.7 V to +5.5 V is required. The power supply to each of the VPOS pins should be decoupled with a 0.1 µF, surface mount ceramic capacitor and a series resistor of 10 Ω. The PWDN pin is shown as grounded. The AD8313 may be disabled by a logic “HI” at this pin. When disabled, the chip current is reduced to about 20 µA from its normal value of 13.7 mA. The logic threshold is at VPOS/2 and the enable func- tion occurs in about 1.8 µs; note, however, that further settling time is generally needed at low input levels. While the input in this case is terminated with a simple 50 Ω broadband resistive match, there are a wide variety of ways in which the input termi- nation can be accomplished. These are discussed in the Input Coupling section. VSET is connected to VOUT to establish a feedback path that controls the overall scaling of the logarithmic amplifier. The load resistance, RL, should not be lower than 5 kΩ in order that the full-scale output of 1.75 V can be generated with the limited available current of 400 µA max. As stated in the Absolute Maximum Ratings, an externally ap- plied overvoltage on the VOUT pin that is outside the range 0 V to VPOS is sufficient to cause permanent damage to the device. If overvoltages are expected on the VOUT pin, a series resistor (RPROT) should be included as shown. A 500 Ω resistor is suffi- cient to protect against overvoltage up to ±5 V; 1000 Ω should be used if an overvoltage of up to ±15 V is expected. Since the output stage is meant to drive loads of no more than 400 µA, this resistor will not impact device performance for more high impedance drive applications (higher output current applications are discussed in the Increasing Output Current section). R2 10 RL = 1M 0.1 F 53.6 680pF 680pF R1 10 0.1 F +VS +VS 8 7 6 5 1 2 3 4 VPOS VOUT INHI INLO VPOS PWDN COMM VSET AD8313 RPROT Figure 27. Basic Connections for Log (RSSI) Mode Operating in the Controller Mode Figure 28 shows the basic connections for operation in control- ler mode. The link between VOUT and VSET is broken and a “setpoint” is applied to VSET. Any difference between VSET and the equivalent input power to the AD8313, will drive VOUT either to the supply rail or close to ground. If VSET is greater than the equivalent input power, VOUT will be driven towards ground and vice versa. VSETPOINT INPUT CONTROLLER OUTPUT R3 10 0.1 F R1 10 0.1 F +VS +VS 8 7 6 5 1 2 3 4 VPOS VOUT INHI INLO VPOS PWDN COMM VSET AD8313 RPROT Figure 28. Basic Connections for Operation in the Controller Mode This mode of operation is useful in applications where the out- put power of an RF power amplifier (PA) is to be controlled by an analog AGC loop (Figure 29). In this mode, a setpoint voltage, proportional in dB to the desired output power, is ap- plied to the VSET pin. A sample of the output power from the PA, via a directional coupler or other means, is fed to the input of the AD8313. SETPOINT CONTROL DAC RFIN VOUT VSET AD8313 DIRECTIONAL COUPLER POWER AMPLIFIER RF IN ENVELOPE OF TRANSMITTED SIGNAL Figure 29. Setpoint Controller Operation VOUT is applied to the gain control terminal of the power ampli- fier. The gain control transfer function of the power amplifier should be an inverse relationship, i.e., increasing voltage de- creases gain. |
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