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AD8323 Folha de dados(PDF) 4 Page - Analog Devices |
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AD8323 Folha de dados(HTML) 4 Page - Analog Devices |
4 / 16 page REV. 0 AD8323 –4– ORDERING GUIDE Model Temperature Range Package Description JA Package Option AD8323ARU –40 °C to +85°C 28-Lead TSSOP 67.7 °C/W* RU-28 AD8323ARU-REEL –40 °C to +85°C 28-Lead TSSOP 67.7 °C/W* RU-28 AD8323-EVAL Evaluation Board *Thermal Resistance measured on SEMI standard 4-layer board. ABSOLUTE MAXIMUM RATINGS * Supply Voltage +VS Pins 5, 9, 10, 19, 20, 23, 27 . . . . . . . . . . . . . . . . . . . . . . 6 V Input Voltages Pins 25, 26 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±0.5 V Pins 1, 2, 3, 6, 7 . . . . . . . . . . . . . . . . . . . . . –0.8 V to +5.5 V Internal Power Dissipation TSSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.9 W Operating Temperature Range . . . . . . . . . . . –40 °C to +85°C Storage Temperature Range . . . . . . . . . . . . –65 °C to +150°C Lead Temperature, Soldering 60 seconds . . . . . . . . . . . 300 °C *Stresses above those listed under Absolute Maximum Ratings may cause perma- nent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. PIN CONFIGURATION TOP VIEW (Not to Scale) 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 AD8323 DATEN GND SDATA VCC CLK VIN– GND VIN+ VCC GND PD VCC SLEEP GND GND BYP VCC VCC VCC VCC GND GND GND GND GND GND OUT– OUT+ CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD8323 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE PIN FUNCTION DESCRIPTIONS Pin No. Mnemonic Description 1 DATEN Data Enable Low Input. This port controls the 8-bit parallel data latch and shift register. A Logic 0-to-1 transition transfers the latched data to the attenuator core (updates the gain) and simulta- neously inhibits serial data transfer into the register. A 1-to-0 transition inhibits the data latch (holds the previous gain state) and simultaneously enables the register for serial data load. 2 SDATA Serial Data Input. This digital input allows for an 8-bit serial (gain) word to be loaded into the internal register with the MSB (Most Significant Bit) first. 3 CLK Clock Input. The clock port controls the serial attenuator data transfer rate to the 8-bit master- slave register. A Logic 0-to-1 transition latches the data bit and a 1-to-0 transfers the data bit to the slave. This requires the input serial data word to be valid at or before this clock transition. 4, 8, 11,12, GND Common External Ground Reference. 13, 16, 17, 18, 22, 24, 28 5, 9, 10, 19, VCC Common Positive External Supply Voltage. A 0.1 µF capacitor must decouple each pin. 20, 23, 27 6 PD Logic “0” powers down the part. Logic “1” powers up the part. 7 SLEEP Low Power Sleep Mode. In the Sleep mode, the AD8323’s supply current is reduced to 4 mA. A Logic “0” powers down the part (High ZOUT State) and a Logic “1” powers up the part. 14 OUT– Negative Output Signal. 15 OUT+ Positive Output Signal. 21 BYP Internal Bypass. This pin must be externally ac-coupled (0.1 µF cap). 25 VIN+ Noninverting Input. DC-biased to approximately VCC/2. For single-ended inverting operation, use a 0.1 µF decoupling capacitor and a 39.2 Ω resistor between V IN+ and ground. 26 VIN– Inverting Input. DC-biased to approximately VCC/2. Should be ac-coupled with a 0.1 µF capacitor. |
Nº de peça semelhante - AD8323 |
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Descrição semelhante - AD8323 |
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