PSPICE Electrical Model

.SUBCKT FDD10AN06A0 2 1 3 ;

rev July 2002

Ca 12 8 7e-10

Cb 15 14 7e-10

Cin 6 8 1.8e-9

Dbody 7 5 DbodyMOD

Dbreak 5 11 DbreakMOD

Dplcap 10 5 DplcapMOD

Ebreak 11 7 17 18 67.2

Eds 14 8 5 8 1

Egs 13 8 6 8 1

Esg 6 10 6 8 1

Evthres 6 21 19 8 1

Evtemp 20 6 18 22 1

It 8 17 1

Lgate 1 9 3.2e-9

Ldrain 2 5 1.0e-9

Lsource 3 7 1.2e-9

RLgate 1 9 32

RLdrain 2 5 10

RLsource 3 7 12

Mmed 16 6 8 8 MmedMOD

Mstro 16 6 8 8 MstroMOD

Mweak 16 21 8 8 MweakMOD

Rbreak 17 18 RbreakMOD 1

Rdrain 50 16 RdrainMOD 1.35e-3

Rgate 9 20 3.6

RSLC1 5 51 RSLCMOD 1e-6

RSLC2 5 50 1e3

Rsource 8 7 RsourceMOD 6e-3

Rvthres 22 8 RvthresMOD 1

Rvtemp 18 19 RvtempMOD 1

S1a 6 12 13 8 S1AMOD

S1b 13 12 13 8 S1BMOD

S2a 6 15 14 13 S2AMOD

S2b 13 15 14 13 S2BMOD

Vbat 22 19 DC 1

ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*250),7))}

.MODEL DbodyMOD D (IS=2E-11 N=1.06 RS=3.3e-3 TRS1=2.4e-3 TRS2=1.1e-6

+ CJO=1.25e-9 M=5.3e-1 TT=4.2e-8 XTI=3.9)

.MODEL DbreakMOD D (RS=2.7e-1 TRS1=1e-3 TRS2=-8.9e-6)

.MODEL DplcapMOD D (CJO=4.7e-10 IS=1e-30 N=10 M=0.44)

.MODEL MmedMOD NMOS (VTO=3.5 KP=5.5 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=3.6)

.MODEL MstroMOD NMOS (VTO=4.25 KP=80 IS=1e-30 N=10 TOX=1 L=1u W=1u)

.MODEL MweakMOD NMOS (VTO=2.92 KP=0.03 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=36 RS=0.1)

.MODEL RbreakMOD RES (TC1=9e-4 TC2=5e-7)

.MODEL RdrainMOD RES (TC1=2.5e-2 TC2=7.8e-5)

.MODEL RSLCMOD RES (TC1=1e-3 TC2=3.5e-5)

.MODEL RsourceMOD RES (TC1=1e-3 TC2=1e-6)

.MODEL RvthresMOD RES (TC1=-5.3e-3 TC2=-1.3e-5)

.MODEL RvtempMOD RES (TC1=-2.6e-3 TC2=1.3e-6)

.MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-8 VOFF=-5)

.MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-5 VOFF=-8)

.MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-2 VOFF=-1.5)

.MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-1.5 VOFF=-2)

.ENDS

Note: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global

Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank

Wheatley.

18

22

+

-

6

8

+

-

5

51

19

8

+

-

17

18

6

8

+

-

5

8

+

-

RBREAK

RVTEMP

VBAT

RVTHRES

IT

17

18

19

22

12

13

15

S1A

S1B

S2A

S2B

CA

CB

EGS

EDS

14

8

13

8

14

13

MWEAK

EBREAK

DBODY

RSOURCE

SOURCE

11

7

3

LSOURCE

RLSOURCE

CIN

RDRAIN

EVTHRES

16

21

8

MMED

MSTRO

DRAIN

2

LDRAIN

RLDRAIN

DBREAK

DPLCAP

ESLC

RSLC1

10

5

51

50

RSLC2

1

GATE

RGATE

EVTEMP

9

ESG

LGATE

RLGATE

20

+

-

+

-

+

-

6

©2012 Fairchild Semiconductor Corporation

FDD10AN06A0_F085 Rev. C1