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AD872ASD Folha de dados(PDF) 5 Page - Analog Devices |
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AD872ASD Folha de dados(HTML) 5 Page - Analog Devices |
5 / 20 page REV. A –5– AD872A 7 17 8 9 10 11 12 13 14 15 16 1 640 44 41 42 43 2 3 4 5 29 39 30 31 32 33 34 35 36 37 38 18 28 19 20 21 22 23 24 25 26 27 AD872A TOP VIEW (NOT TO SCALE) OTR MSB AVDD AGND DGND CLK BIT 12 (LSB) AGND DRGND DVDD BIT 11 DRVDD DRVDD DRGND OEN NC NC NC NC NC NC NC NC = NO CONNECT PIN DESCRIPTION DIP LCC Symbol Pin No. Pin No. Type Name and Function VINA 1 1 AI (+) Analog Input Signal on the differential input amplifier. VINB 2 2 AI (–) Analog Input Signal on the differential input amplifier. AVSS 3, 25 5, 40 P –5 V Analog Supply. AVDD 4 6, 38 P +5 V Analog Supply. AGND 5, 24 9, 36 P Analog Ground. DGND 6, 23 10 P Digital Ground. DVDD 7, 22 33 P +5 V Digital Supply. BIT 12 (LSB) 8 16 DO Least Significant Bit. BIT 2–BIT 11 18–9 26–17 DO Data Bits 2 through 11. MSB 19 29 DO Inverted Most Significant Bit. Provides twos complement output data format. OTR 20 30 DO Out of Range is Active HIGH on the leading edge of Code 0 or the trailing edge of Code 4096. See Output Data Format Table III. CLK 21 31 DI Clock Input. The AD872A will initiate a conversion on the rising edge of the clock input. See the Timing Diagram for details. REF OUT 26 41 AO +2.5 V Reference Output. Tie to REF IN for normal operation. REF GND 27 42 AI Reference Ground. REF IN 28 43 AI Reference Input. +2.5 V input gives ±1 V full-scale range. DRVDD N/A 12, 32 P +5 V Digital Supply for the output drivers. NC N/A 3, 4, 7, 8, 14, 15, No Connect. 28, 35, 37, 39, 44 DRGND N/A 11, 34 P Digital Ground for the output drivers. (See section on Power Supply Decoupling for details on DRVDD and DRGND.) OEN N/A 13 DI Output Enable. See the Three State Output Timing Diagram for details. BIT 1 N/A 27 DO Most Significant Bit. TYPE: AI = Analog Input; AO = Analog Output; DI = Digital Input; DO = Digital Output; P = Power; N/A = Not Available on 28-lead DIP. Only available on 44-terminal surface mount package. PIN CONFIGURATIONS 28-Lead Ceramic DIP 44-Terminal LCC 14 13 12 11 17 16 15 20 19 18 10 9 8 1 2 3 4 7 6 5 TOP VIEW (Not to Scale) 28 27 26 25 24 23 22 21 AD872A VINA AVSS REF OUT REF GND REF IN VINB AVSS AVDD DVDD DGND AGND AGND DGND DVDD BIT 12 (LSB) BIT 11 BIT 10 MSB OTR CLK BIT 9 BIT 8 BIT 7 BIT 6 BIT 2 BIT 5 BIT 4 BIT 3 |
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