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AD9100AD Folha de dados(PDF) 6 Page - Analog Devices |
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AD9100AD Folha de dados(HTML) 6 Page - Analog Devices |
6 / 12 page AD9100 REV. B –6– Acquisition Time Acquisition time is the amount of time it takes the AD9100 to reacquire the analog input when switching from hold to track mode. The interval starts at the 50% clock transition point and ends when the input signal is reacquired to within a specified error band at the hold capacitor. The hold to track switch delay (tDHt) cannot be subtracted from this acquisition time because it is a charging time delay that occurs when moving from hold to track; this is typically 4 ns to 6 ns and is the longest delay. Therefore, the track time required for the AD9100 is the acquisition time minus the aper- ture delay time. Note that the acquisition time is defined as the settled voltage at the hold capacitor and does not include the delay and settling time of the output buffer. The example below illustrates why the output buffer amplifier does not contribute to the overall AD9100 acquisition time. CH VCH INPUT BUFFER VOUT VIN TRACK HOLD TIME PEAK TRANSIENT SEEN BY OUTPUT BUFFER tDHT 6ns VCH VOUT ACQUISITION TIME AT CH TO X% OUTPUT BUFFER tS Figure 13. Acquisition Time Diagram The exaggerated illustration in Figure 13 shows that VCH has settled to within x% of its final value, but VOUT (due to slew rate limitations, finite BW, power supply ringing, etc.) has not settled during the track time. However, since the output buffer always “tracks” the front end circuitry, it “catches up” during the hold time and directly superimposes itself (less about 600 ps of analog delay) to VCH. Since the small-signal settling time of the output buffer is about 1.8 ns to ±1 mV and is significantly less than the specified hold time, acquisition time should be referenced to the hold capacitor. Note that most of the hold settling time and output acquisition time are due to the input buffer and the switch network. For track time, the output buffer contributes only about 5 ns of the total; in hold mode, it contributes only 1.8 ns (as stated above). A stricter definition of acquisition time would total the acquisi- tion and hold times to a defined accuracy. To obtain 12 bit + distortion levels and 30 MSPS operation, the recommended track and hold times are 20 ns and 13.5 ns, respectively. To drive an 8-bit flash converter with a 2 V p-p full-scale input, hold time to 1 LSB accuracy will be limited primarily by the encoder, rather than by the AD9100. This makes it possible to reduce track time to approximately 13 ns, with hold time chosen to optimize the encoder’s performance. THEORY OF OPERATION The AD9100 utilizes a new track and hold architecture. Previ- ous commercially available high speed track and holds used an open loop input buffer, followed by a diode bridge, hold capaci- tor, and output buffer (closed or open loop) with a FET device connected to the hold capacitor. This architecture required mixed device technology and, usually, hybrid construction. The sampling rate of these hybrids has been limited to 20 MSPS for 12-bit accuracy. Distortion generated in the front-end amplifier/ bridge limited the dynamic range performance to the “mid-70 dBfs” for analog input signals of less than 10 MHz. Broadband and switch-generated noise limited the SNR of previous track and holds to about 70 dB. The AD9100 is a monolithic device using a high frequency complementary bipolar process to achieve new levels of high speed precision. Its patent pending architecture breaks from the traditional architecture described above. (See the block diagram on the first page.) The switching type bridge has been integrated into the first stage closed loop input amplifier. This innovation provides error (distortion) correction for both the switch and amplifier, while still achieving slew rates representative of an open-loop design. In addition, acquisition slew current for the hold capacitor is higher than standard diode bridge and switch configurations, removing a main contributor to the limits of maximum sampling rate and input frequency. Switching circuits in the device use current steering (versus voltage switching) to provide improved isolation between the switch and analog sections. This results in low aperture time sensitivity to the analog input signal, and reduced power supply and analog switching noise. Track to hold peak switching tran- sient is typically only 6 mV and settles to less than 1 mV in 7 ns. In addition, pedestal sensitivity to analog input voltage is very low (0.6 mV/V) and being first order linear does not significantly affect distortion. The closed-loop output buffer includes zero voltage bias current cancellation, which results in high-temperature droop rates equivalent to those found in FET type inputs. The buffer also provides first order quasistatic bias correction resulting in an extremely high input resistance and very low droop sensitivity vs. input voltage level (typically less than 1.5 mV/V– µs.) This closed-loop architecture inherently provides high speed loop correction and results in low distortion under heavy loads. The extremely fast time constant linearity (7 ns to 0.01% for a 2 V step) ensures that the output buffer does not limit the AD9100 sampling rate or analog input frequency. (The acquisi- tion and settling time are primarily limited only by the input amplifier and switch.) The output is transparent to the overall AD9100 hold mode distortion levels for loads as low as 250 Ω. Full-scale track and acquisition slew rates achieved by the AD9100 are 800 and 1000 V/ µs, respectively. When combined with excellent phase margin (typically 5% overshoot), wide bandwidth, and dc gain accuracy, acquisition time to 0.01% is only 16 ns. Though not production tested, settling to 14-bit accuracy (–86 dB distortion @ 2.3 MHz) can be inferred to be 20 ns. |
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