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ADF4106 Folha de dados(PDF) 8 Page - Analog Devices |
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ADF4106 Folha de dados(HTML) 8 Page - Analog Devices |
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8 / 20 page  REV. 0 ADF4106 –8– PRESCALER OUTPUT FREQUENCY 3.5 3.0 0 50 300 100 150 200 250 2.0 1.5 1.0 0.5 2.5 VDD = 3V VP = 3V TPC 13. DIDD vs. Prescaler Output Frequency VCP – V 6 0 –6 0 5.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 4 2 –2 –4 VP = 5V ICP = 5mA TPC 14. Charge Pump Output Characteristics CIRCUIT DESCRIPTION REFERENCE INPUT SECTION The Reference Input stage is shown in Figure 2. SW1 and SW2 are normally-closed switches. SW3 is normally-open. When Powerdown is initiated, SW3 is closed and SW1 and SW2 are opened. This ensures that there is no loading of the REFIN pin on power-down. POWER-DOWN CONTROL 100k NC REFIN NC NO SW1 SW2 SW3 BUFFER TO R COUNTER NC = NO CONNECT Figure 2. Reference Input Stage RF INPUT STAGE The RF input stage is shown in Figure 3. It is followed by a 2-stage limiting amplifier to generate the CML clock levels needed for the prescaler. AVDD 500 1.6V RF IN A RF IN B 500 AGND BIAS GENERATOR Figure 3. RF Input Stage PRESCALER (P/P + 1) The dual modulus prescaler (P/P + 1), along with the A and B counters, enables the large division ratio, N, to be realized (N = BP + A). The dual-modulus prescaler, operating at CML levels, takes the clock from the RF input stage and divides it down to a manageable frequency for the CMOS A and B counters. The prescaler is programmable. It can be set in soft- ware to 8/9, 16/17, 32/33 or 64/65. It is based on a synchronous 4/5 core. There is a minimum divide ratio possible for fully contiguous output frequencies. This minimum is determined by P, the prescaler value and is given by: (P 2 – P). A AND B COUNTERS The A and B CMOS counters combine with the dual modulus prescaler to allow a wide ranging division ratio in the PLL feed- back counter. The counters are specified to work when the prescaler output is 300 MHz or less. Thus, with an RF input frequency of 4.0 GHz, a prescaler value of 16/17 is valid but a value of 8/9 is not valid. Pulse Swallow Function The A and B counters, in conjunction with the dual modulus prescaler make it possible to generate output frequencies which are spaced only by the Reference Frequency divided by R. The equation for the VCO frequency is as follows: fP B A f R VCO REFIN =× + × [( ) ] fVCO Output Frequency of external voltage controlled oscillator (VCO). P Preset modulus of dual modulus prescaler (8/9, 16/17, etc.,). B Preset Divide Ratio of binary 13-bit counter (3 to 8191). A Preset Divide Ratio of binary 6-bit swallow counter (0 to 63). fREFIN External reference frequency oscillator. |
Nº de peça semelhante - ADF4106 |
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Descrição semelhante - ADF4106 |
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