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ADMCF341BR Folha de dados(PDF) 11 Page - Analog Devices |
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ADMCF341BR Folha de dados(HTML) 11 Page - Analog Devices |
11 / 36 page REV. 0 ADMCF341 –11– PWMTRIP OR PWMSWT (0) OVER- CURRENT TRIP PWM SHUTDOWN CONTROLLER ANALOG BLOCK PWMTRIP ISENSE2 ISENSE1 ISENSE3 PWMSEG (8...0) OUTPUT CONTROL UNIT GATE DRIVE UNIT CLK PWM DUTY CYCLE REGISTERS PWM CONFIGURATION REGISTERS TO INTERRUPT CONTROLLER THREE-PHASE PWM TIMING UNIT CLK RESET SYNC SYNC PWMSYNC CLKOUT AH AL BH BL CH CL PWMGATE (9...0) PWMTM (15...0) PWMDT (9...0) PWMPD (9...0) PWMSYNCWT (7...0) MODECTRL (6) PWMCHA (15...0) PWMCHB (15...0) PWMCHC (15...0) Figure 6. Overview of the PWM Controller of the ADMCF341 The ADMCF341 sets all internal stack pointers to the empty stack condition, masks all interrupts, clears the MSTAT register, and performs a full reset of all of the motor control peripherals. Following a power-up, it is possible to initiate a DSP core and motor control peripheral reset by pulling the RESET pin low. The RESET signal must be the minimum pulsewidth specifica- tion, tRSP. Following the reset sequence, the DSP core starts executing code from the internal PM ROM located at 0x0800. DSP Control Registers The DSP core has a system control register, SYSCNTL, memory-mapped at DM (0x3FFF). SPORT1 must be configured as a serial port by setting Bit 10. SPORT0 and SPORT1 are enabled by setting Bit 11 and Bit 12. The DSP core has a wait state control register, MEMWAIT, memory-mapped at DM (0x3FFE). The default value of this register is 0xFFFF. For proper operation of the ADMCF341, this register must always contain the value 0x8000. This value sets the minimum access time to the program memory. The configurations of both the SYSCNTL and MEMWAIT regis- ters of the ADMCF341 are shown at the end of the data sheet. THREE-PHASE PWM CONTROLLER Overview The PWM generator block of the ADMCF341 is a flexible, programmable three-phase PWM waveform generator that can be programmed to generate the required switching patterns to drive a three-phase voltage source inverter for ac induction motors (ACIM) or permanent magnet synchronous motors (PMSM). In addition, the PWM block contains special func- tions that considerably simplify the generation of the required PWM switching patterns for control of brushless dc motors (BDCM), including electronically commutated motors (ECM). The six PWM output signals consist of three high side drive signals (AH, BH, and CH) and three low side drive signals (AL, BL, and CL). The switching frequency, dead time, and minimum pulsewidths of the generated PWM patterns are pro- grammable using, respectively, the PWMTM, PWMDT, and PWMPD registers. In addition, three registers (PWMCHA, PWMCHB, and PWMCHC) control the duty cycles of the three pairs of PWM signals. Each of the six PWM output signals can be enabled or disabled by separate output enable bits of the PWMSEG register. In addition, three control bits of the PWMSEG register permit crossover of the two signals of a PWM pair for easy control of ECM or BDCM. In crossover mode, the high side PWM signals are diverted to the complementary low side output and the low side signals are diverted to the corresponding high side outputs. In many applications, there is a need to provide an isolation barrier in the gate-drive circuits that turn on the power devices of the inverter. In general, there are two common isolation techniques: optical isolation using optocouplers, and trans- former isolation using pulse transformers. The PWM controller of the ADMCF341 permits mixing of the output PWM signals with a high-frequency chopping signal to permit an easy inter- face to such pulse transformers. The features of this gate-drive chopping mode can be controlled by the PWMGATE register. There is an 8-bit value within the PWMGATE register that directly controls the chopping frequency. In addition, high- frequency chopping can be independently enabled for the high side and the low side outputs using separate control bits in the PWMGATE register. |
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