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ADV101 Folha de dados(PDF) 7 Page - Analog Devices

Nome de Peças ADV101
Descrição Electrónicos  CMOS 80 MHz, Triple 8-Bit Video DAC
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Fabricante Electrônico  AD [Analog Devices]
Página de início  http://www.analog.com
Logo AD - Analog Devices

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ADV101
–7–
REV. B
If we, therefore, have a graphics system with a 1024
× 1024
resolution, a noninterlaced 60 Hz refresh rate and a retrace fac-
tor of 0.8, then:
Dot Rate = 1024
× 1024 × 60/0.8
Dot Rate = 78.6 MHz
Video Synchronization and Control
The ADV101 has a single composite video sync (SYNC) input
control. Many graphics processors and CRT controllers have
the ability of generating horizontal sync (HSYNC), vertical sync
(VSYNC) and composite SYNC.
In a graphics system which does not automatically generate a
composite SYNC signal, the inclusion of some additional logic
circuitry will enable the generation of a composite SYNC signal.
The ISYNC current output is typically connected directly to the
IOG output, thus encoding video synchronization information
onto the green video channel. If it is not required to encode sync
information onto the ADV101, the SYNC input should be tied
to logic low and ISYNC should be connected to analog GND.
Reference Input
An external 1.23 V voltage reference is required to drive the
ADV101. The AD589 from Analog Devices is an ideal choice of
reference. It is a two-terminal, low cost, temperature compen-
sated bandgap voltage reference which provides a fixed 1.23 V
output voltage for input currents between 50
µA and 5 mA. Fig-
ure 4 shows a typical reference circuit connection diagram. The
voltage reference gets its current drive from the ADV101’s VAA
through an external 1 k
Ω resistor to the V
REF pin. A 0.1 µF ce-
ramic capacitor is required between the COMP and VAA. This is
necessary so as to provide compensation for the internal refer-
ence amplifier.
The required CLOCK frequency is thus 78.6 MHz.
All video data and control inputs are latched into the ADV101
on the rising edge of CLOCK, as previously described in the
“Digital Inputs” section. It is recommended that the CLOCK
input to the ADV101 be driven by a TTL buffer (e.g., 74F244).
Table I. Video Output Truth Table
IOG
IOR, IOB
REF
DAC
Description
(mA)
1
(mA)
WHITE
SYNC
BLANK
Input Data
WHITE LEVEL
26.67
19.05
1
1
1
xxH
WHITE LEVEL
26.67
19.05
0
1
1
FFH
VIDEO
video + 9.05
video + 1.44
0
1
1
data
VIDEO to BLANK
video + 1.44
video + 1.44
0
0
1
data
BLACK LEVEL
9.05
1.44
0
1
1
00H
BLACK to BLANK
1.44
1.44
0
0
1
00H
BLANK LEVEL
7.62
0
0
1
0
xxH
SYNC LEVEL
0
0
0
0
0
xxH
NOTE
1Typical with full-scale IOG = 26.67 mA. V
REF = 1.235 V, RSET = 560 Ω, ISYNC connected to IOG.
92.5 IRE
7.5 IRE
40 IRE
WHITE LEVEL
BLACK LEVEL
BLANK LEVEL
SYNC LEVEL
19.05
0.714
26.67
1.000
1.44
0.054
9.05
0.340
0
0
7.62
0.286
0
0
mA
V
mA
V
RED, BLUE
GREEN
NOTES
1. OUTPUTS CONNECTED TO A DOUBLY TERMINATED 75
Ω LOAD.
2. V
= 1.235V, R
= 560
Ω, I
CONNECTED TO IOG.
REF
SET
SYNC
3. RS-343A LEVELS AND TOLERANCES ASSUMED ON ALL LEVELS.
Figure 3. RGB Video Output Waveform


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