ADV476

REV. B

–5–

PIN FUNCTION DESCRIPTION

Pin

Mnemonic

Function

BLANK

Composite blank control input (TTL compatible). A logic zero on this control input drives the analog outputs to

the blanking level, as shown in Table V. The BLANK signal is latched on the rising edge of PCLK. While

BLANK

is a logical zero, the pixel inputs are ignored.

PCLK

Clock input (TTL compatible). The rising edge of PCLK latches the P0–P7 data inputs and the BLANK control

input. It is typically the pixel clock rate of the video system. PCLK should be driven by a dedicated TTL buffer.

P0–P7

Pixel select inputs (TTL compatible). These inputs specify, on a pixel basis, which one of the 256 entries in the

color palette RAM is to be used to provide color information. P0–P7 pixel select inputs are latched on the rising

edge of PCLK. P0 is the LSB. Unused pixel select inputs should be connected to GND.

RED, GREEN,

Red, green and blue current outputs. These high impedance current sources are capable of directly driving a

BLUE

doubly terminated 75

Ω coaxial cable, as shown in Figure 4a. All three current outputs should have similar out-

put loads whether or not they are all being used.

Analog power supply (5 V

± 10%).

GND

Analog ground.

Current reference input. The relationship between the current input and the full scale output voltage of the

DACs is given by the following expression:

WR

Write control input (TTL compatible). WR must be at logical zero when writing data to the device. D0–D7 data

is latched on the rising edge of WR. See Figure 1.

RD

Read control input (TTL compatible). RD must both be at logical zero when reading data from the device.

See Figure 1.

RS0, RS1

Command control inputs (TTL compatible). RS0 and RS1 specify the type of read or write operation being car-

ried out, i.e., address register or color palette RAM read or write operations. See Tables I, II, III.

D0–D7

Data bus (TTL compatible). Data is transferred to and from the address register and the color palette RAM over

this 8-bit bidirectional data bus. D0 is the least significant bit.

TERMINOLOGY

Blanking Level

The level separating the SYNC portion from the Video portion

of the waveform. Usually referred to as the Front Porch or Back

Porch. At 0 IRE Units, it is the level which will shut off the pic-

ture tube, resulting in the blackest possible picture.

Color Video (RGB)

This usually refers to the technique of combining the three pri-

mary colors of Red, Green and Blue to produce color pictures

within the usual spectrum. In RGB monitors, three DACs are

required, one for each color.

Gray Scale

The discrete levels of video signal between Reference Black and

Reference White levels. An 8-bit DAC contains 256 different

levels while a 6-bit DAC contains 64.

Raster Scan

The most basic method of sweeping a CRT one line at a time to

generate and display images.

Reference Black Level

The maximum negative polarity amplitude of the video signal.

Reference White Level

The maximum positive polarity amplitude of the video signal.

Video Signal

That portion of the composite video signal which varies in gray

scale levels between Reference White and Reference Black. Also

referred to as the picture signal, this is the portion which may be

visually observed.